文件名称:shiyan4_2
介绍说明－－下载内容均来自于网络，请自行研究使用
哈工大计算机学院2014年夏季学期设计与实践实验4.2 FPGA时钟信号功能测试-FPGA CLK design from hit computer science
(系统自动生成,下载前可以参看下载内容)
下载文件列表
shiyan4_2
.........\_xmsgs
.........\......\netgen.xmsgs
.........\......\pn_parser.xmsgs
.........\......\xst.xmsgs
.........\ipcore_dir
.........\iseconfig
.........\.........\shiyan4_2.projectmgr
.........\.........\shiyan4_2.xreport
.........\netgen
.........\......\synthesis
.........\......\.........\shiyan4_2_synthesis.nlf
.........\......\.........\shiyan4_2_synthesis.vhd
.........\pepExtractor.prj
.........\shiyan4_2.cmd_log
.........\shiyan4_2.gise
.........\shiyan4_2.lso
.........\shiyan4_2.ngc
.........\shiyan4_2.ngr
.........\shiyan4_2.prj
.........\shiyan4_2.stx
.........\shiyan4_2.syr
.........\shiyan4_2.vhd
.........\shiyan4_2.xise
.........\shiyan4_2.xst
.........\shiyan4_2_envsettings.html
.........\shiyan4_2_summary.html
.........\shiyan4_2_xst.xrpt
.........\test.vhd
.........\webtalk_pn.xml
.........\xst
.........\...\dump.xst
.........\...\........\shiyan4_2.prj
.........\...\projnav.tmp
.........\...\work
.........\...\....\work.vdbl
.........\...\....\work.vdbx