文件名称:MIPSCPU
- 所属分类：
- 微处理器(ARM/PowerPC等)
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2014-05-26
- 文件大小：
- 166kb
- 下载次数：
- 0次
- 提 供 者：
- zhq****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
这是verilog实现的MIPS多周期CPU在modelsim下面仿真通过-This is achieved verilog CPU MIPS multi-cycle simulation in modelsim below by
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下载文件列表
12061115_周其林.docx
Project6(finish)\alu.v
................\be_load.v
................\be_save.v
................\code.txt
................\controller.v
................\dm.v
................\ext.v
................\gpr.v
................\head_mips.v
................\im.v
................\mips.cr.mti
................\mips.mpf
................\mips.v
................\mux.v
................\npc.v
................\pc.v
................\testbench.v
................\vsim.wlf
................\wave1.bmp
................\wave2.bmp
................\.ork\alu\verilog.asm64
................\....\...\verilog.rw64
................\....\...\_primary.dat
................\....\...\_primary.dbs
................\....\...\_primary.vhd
................\....\be_load\verilog.asm64
................\....\.......\verilog.rw64
................\....\.......\_primary.dat
................\....\.......\_primary.dbs
................\....\.......\_primary.vhd
................\....\...save\verilog.asm64
................\....\.......\verilog.rw64
................\....\.......\_primary.dat
................\....\.......\_primary.dbs
................\....\.......\_primary.vhd
................\....\controller\verilog.asm64
................\....\..........\verilog.rw64
................\....\..........\_primary.dat
................\....\..........\_primary.dbs
................\....\..........\_primary.vhd
................\....\dm\verilog.asm64
................\....\..\verilog.rw64
................\....\..\_primary.dat
................\....\..\_primary.dbs
................\....\..\_primary.vhd
................\....\gpr\verilog.asm64
................\....\...\verilog.rw64
................\....\...\_primary.dat
................\....\...\_primary.dbs
................\....\...\_primary.vhd
................\....\im\verilog.asm64
................\....\..\verilog.rw64
................\....\..\_primary.dat
................\....\..\_primary.dbs
................\....\..\_primary.vhd
................\....\mips\verilog.asm64
................\....\....\verilog.rw64
................\....\....\_primary.dat
................\....\....\_primary.dbs
................\....\....\_primary.vhd
................\....\.ux32\verilog.asm64
................\....\.....\verilog.rw64
................\....\.....\_primary.dat
................\....\.....\_primary.dbs
................\....\.....\_primary.vhd
................\....\...5\verilog.asm64
................\....\....\verilog.rw64
................\....\....\_primary.dat
................\....\....\_primary.dbs
................\....\....\_primary.vhd
................\....\npc\verilog.asm64
................\....\...\verilog.rw64
................\....\...\_primary.dat
................\....\...\_primary.dbs
................\....\...\_primary.vhd
................\....\pc\verilog.asm64
................\....\..\verilog.rw64
................\....\..\_primary.dat
................\....\..\_primary.dbs
................\....\..\_primary.vhd
................\....\sign_ext\verilog.asm64
................\....\........\verilog.rw64
................\....\........\_primary.dat
................\....\........\_primary.dbs
................\....\........\_primary.vhd
................\....\testbench_mips\verilog.asm64
................\....\..............\verilog.rw64
................\....\..............\_primary.dat
................\....\..............\_primary.dbs
................\....\..............\_primary.vhd
................\....\zero_ext\verilog.asm64
................\....\........\verilog.rw64
................\....\........\_primary.dat
................\....\........\_primary.dbs
................\....\........\_primary.vhd
................\....\_info
................\....\_vmake
................\....\alu
................\....\be_load