文件名称:vhdl
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译码器设计
实现3-8译码器的门级和行为级设计；完成3-8译码器的门级和行为级设计的仿真，并下载到开发板进行验证。
用拨挡开关K1，K2，K3作为输入的三位二进制码，输出的8位码分别用LED1~LED8 显示-Achieve 3-8 decoder gate-level and behavioral level design complete the 3-8 decoder gate-level simulation and behavioral level design, and downloaded to the development board for verification. Using DIP switch block K1, K2, K3 of the three binary code as input, output 8 yards respectively show LED1 ~ LED8
实现3-8译码器的门级和行为级设计；完成3-8译码器的门级和行为级设计的仿真，并下载到开发板进行验证。
用拨挡开关K1，K2，K3作为输入的三位二进制码，输出的8位码分别用LED1~LED8 显示-Achieve 3-8 decoder gate-level and behavioral level design complete the 3-8 decoder gate-level simulation and behavioral level design, and downloaded to the development board for verification. Using DIP switch block K1, K2, K3 of the three binary code as input, output 8 yards respectively show LED1 ~ LED8
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vhdl.doc