加法计数器的设计 任意进制的计数器设计-LIBRARY IEEE

USE IEEE.STD_LOGIC_1164.ALL

ENTITY sun IS

PORT(ENA,CLK_IN,CLR:IN STD_LOGIC

　　 Y:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)

　　 )

END sun

ARCHITECTURE A OF sun IS

SIGNAL CLK:STD_LOGIC

SIGNAL TEMP:INTEGER RANGE 0 TO 9

BEGIN

CLOCK:PROCESS(CLK_IN)

VARIABLE CLOCK_BUFFER:STD_LOGIC

VARIABLE COUNT_TIME:INTEGER RANGE 0 TO 1999999

BEGIN

IF CLK_IN EVENT AND CLK_IN= 1 THEN

IF COUNT_TIME=1999999 THEN

COUNT_TIME:=0

CLOCK_BUFFER:=NOT CLOCK_BUFFER

ELSE

COUNT_TIME:=COUNT_TIME+1

END IF

END IF

CLK<=CLOCK_BUFFER

END PROCESS

COUNT:PROCESS(CLR,CLK,ENA)

VARIABLE Q:INTEGER RANGE 0 TO 10

BEGIN

IF(CLR= 0 )THEN

Q:=0

ELSE

IF CLK EVENT AND CLK= 1 THEN

IF ENA= 1 THEN

Q:=Q+1

IF(Q=10)THEN