文件名称:21_ds1302
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基于FPGA与DS1302时钟芯片采用Verilog HDL语言编写的数字时钟实现-Based on FPGA and DS1302 clock chip using Verilog HDL language of the digital clock to achieve
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下载文件列表
21_ds1302\ds1302.asm.rpt
.........\ds1302.done
.........\ds1302.fit.rpt
.........\ds1302.fit.smsg
.........\ds1302.fit.summary
.........\ds1302.flow.rpt
.........\ds1302.map.rpt
.........\ds1302.map.summary
.........\ds1302.pin
.........\ds1302.pof
.........\ds1302.qpf
.........\ds1302.qsf
.........\ds1302.sof
.........\ds1302.sta.rpt
.........\ds1302.sta.summary
.........\.b\ds1302.amm.cdb
.........\..\ds1302.asm.qmsg
.........\..\ds1302.asm.rdb
.........\..\ds1302.asm_labs.ddb
.........\..\ds1302.cbx.xml
.........\..\ds1302.cmp.bpm
.........\..\ds1302.cmp.cdb
.........\..\ds1302.cmp.hdb
.........\..\ds1302.cmp.kpt
.........\..\ds1302.cmp.logdb
.........\..\ds1302.cmp.rdb
.........\..\ds1302.cmp_merge.kpt
.........\..\ds1302.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
.........\..\ds1302.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd
.........\..\ds1302.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
.........\..\ds1302.db_info
.........\..\ds1302.fit.qmsg
.........\..\ds1302.hier_info
.........\..\ds1302.hif
.........\..\ds1302.idb.cdb
.........\..\ds1302.lpc.html
.........\..\ds1302.lpc.rdb
.........\..\ds1302.lpc.txt
.........\..\ds1302.map.bpm
.........\..\ds1302.map.cdb
.........\..\ds1302.map.hdb
.........\..\ds1302.map.kpt
.........\..\ds1302.map.logdb
.........\..\ds1302.map.qmsg
.........\..\ds1302.map_bb.cdb
.........\..\ds1302.map_bb.hdb
.........\..\ds1302.map_bb.logdb
.........\..\ds1302.pre_map.cdb
.........\..\ds1302.pre_map.hdb
.........\..\ds1302.rpp.qmsg
.........\..\ds1302.rtlv.hdb
.........\..\ds1302.rtlv_sg.cdb
.........\..\ds1302.rtlv_sg_swap.cdb
.........\..\ds1302.sgate.rvd
.........\..\ds1302.sgate_sm.rvd
.........\..\ds1302.sgdiff.cdb
.........\..\ds1302.sgdiff.hdb
.........\..\ds1302.sld_design_entry_dsc.sci
.........\..\ds1302.smart_action.txt
.........\..\ds1302.sta.qmsg
.........\..\ds1302.sta.rdb
.........\..\ds1302.sta_cmp.8_slow_1200mv_85c.tdb
.........\..\ds1302.syn_hier_info
.........\..\ds1302.tiscmp.fastest_slow_1200mv_0c.ddb
.........\..\ds1302.tiscmp.fastest_slow_1200mv_85c.ddb
.........\..\ds1302.tiscmp.fast_1200mv_0c.ddb
.........\..\ds1302.tiscmp.slow_1200mv_0c.ddb
.........\..\ds1302.tiscmp.slow_1200mv_85c.ddb
.........\..\ds1302.tis_db_list.ddb
.........\..\ds1302.tmw_info
.........\..\logic_util_heursitic.dat
.........\..\ds1302.sld_design_entry.sci
.........\incremental_db\README
.........\..............\compiled_partitions\ds1302.db_info
.........\..............\...................\ds1302.root_partition.cmp.cdb
.........\..............\...................\ds1302.root_partition.cmp.dfp
.........\..............\...................\ds1302.root_partition.cmp.hdb
.........\..............\...................\ds1302.root_partition.cmp.kpt
.........\..............\...................\ds1302.root_partition.cmp.logdb
.........\..............\...................\ds1302.root_partition.cmp.rcfdb
.........\..............\...................\ds1302.root_partition.map.cdb
.........\..............\...................\ds1302.root_partition.map.dpi
.........\..............\...................\ds1302.root_partition.map.hbdb.cdb
.........\..............\...................\ds1302.root_partition.map.hbdb.hb_info
.........\..............\...................\ds1302.root_partition.map.hbdb.hdb
.........\..............\...................\ds1302.root_partition.map.hbdb.sig
.........\..............\...................\ds1302.root_partition.map.hdb
.........\..............\...................\ds1302.root_partition.map.kpt
.........\source\cmd_control_module.v
.........\......\ds1302_module.v
.........\......\function_module.v
.........\......\rtc_control_module.v
.........\......\rtc_interface.v
.........\tcl\21_osh.tcl
.........\incremental_db\compiled_partitions
.........\db
.........\incremental_db
.........\source
.........\tcl
21_ds1302