文件名称:controller_core

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2013-06-17
  • 文件大小:
  • 13.13mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 涂*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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做SD卡,进行SD卡里内容的读写,读取SD卡里的音频内容,并在FPGA板子上进行播放-Do SD card reader for SD card contents, read SD card audio content, and the FPGA board for playback. . .
(系统自动生成,下载前可以参看下载内容)

下载文件列表





controller_core

...............\.sopc_builder

...............\.............\filters.xml

...............\.............\install.ptf

...............\.............\install2.ptf

...............\.............\preferences.xml

...............\address.v

...............\clk_management.bdf

...............\clk_management.bsf

...............\cmd_comb.bsf

...............\cmd_comb.v

...............\cmd_comb.v.bak

...............\controller_core.asm.rpt

...............\controller_core.bdf

...............\controller_core.done

...............\controller_core.dpf

...............\controller_core.fit.rpt

...............\controller_core.fit.smsg

...............\controller_core.fit.summary

...............\controller_core.flow.rpt

...............\controller_core.jdi

...............\controller_core.map.rpt

...............\controller_core.map.smsg

...............\controller_core.map.summary

...............\controller_core.pin

...............\controller_core.qpf

...............\controller_core.qsf

...............\controller_core.sof

...............\controller_core.sta.rpt

...............\controller_core.sta.summary

...............\cpu_0.ocp

...............\cpu_0.sdc

...............\cpu_0.v

...............\cpu_0_ic_tag_ram.mif

...............\cpu_0_jtag_debug_module_sysclk.v

...............\cpu_0_jtag_debug_module_tck.v

...............\cpu_0_jtag_debug_module_wrapper.v

...............\cpu_0_mult_cell.v

...............\cpu_0_ociram_default_contents.mif

...............\cpu_0_oci_test_bench.v

...............\cpu_0_rf_ram_a.mif

...............\cpu_0_rf_ram_b.mif

...............\cpu_0_test_bench.v

...............\CRC.v

...............\CS.v

...............\db

...............\..\altsyncram_0a02.tdf

...............\..\altsyncram_18c1.tdf

...............\..\altsyncram_40g1.tdf

...............\..\altsyncram_50g1.tdf

...............\..\altsyncram_cjd1.tdf

...............\..\altsyncram_r9g1.tdf

...............\..\altsyncram_u972.tdf

...............\..\controller_core.amm.cdb

...............\..\controller_core.asm.qmsg

...............\..\controller_core.asm.rdb

...............\..\controller_core.asm_labs.ddb

...............\..\controller_core.cbx.xml

...............\..\controller_core.cmp.bpm

...............\..\controller_core.cmp.cbp

...............\..\controller_core.cmp.cdb

...............\..\controller_core.cmp.hdb

...............\..\controller_core.cmp.kpt

...............\..\controller_core.cmp.logdb

...............\..\controller_core.cmp.rdb

...............\..\controller_core.cmp_merge.kpt

...............\..\controller_core.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd

...............\..\controller_core.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd

...............\..\controller_core.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd

...............\..\controller_core.db_info

...............\..\controller_core.fit.qmsg

...............\..\controller_core.hier_info

...............\..\controller_core.hif

...............\..\controller_core.idb.cdb

...............\..\controller_core.lpc.html

...............\..\controller_core.lpc.rdb

...............\..\controller_core.lpc.txt

...............\..\controller_core.map.bpm

...............\..\controller_core.map.cbp

...............\..\controller_core.map.cdb

...............\..\controller_core.map.hdb

...............\..\controller_core.map.kpt

...............\..\controller_core.map.logdb

...............\..\controller_core.map.qmsg

...............\..\controller_core.map_bb.cdb

...............\..\controller_core.map_bb.hdb

...............\..\controller_core.map_bb.logdb

...............\..\controller_core.pre_map.cdb

...............\..\controller_core.pre_map.hdb

...............\..\controller_core.rtlv.hdb

...............\..\controller_core.rtlv_sg.cdb

...............\..\controller_core.rtlv_sg_swap.cdb

...............\..\controller_core.sgdiff.cdb

...............\..\controller_core.sgdiff.hdb

...............\..\controller_core.sld_design_entry.sci

...............\..\controller_core.sld_design_entry_dsc.sci

...............\..\controller_core.smart_action.txt

...............\..\controller_core.smp_dump.txt

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