文件名称:u-c
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通过控制机控制CH376 USB芯片达到从机模式通信的目的，采用了低级建模的思想-By controlling the motor control chip CH376 USB slave mode to achieve the purpose of communication, the idea of using a low-level modeling
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下载文件列表
u-c\add_clk.bsf
...\add_clk.v
...\db\logic_util_heursitic.dat
...\..\prev_cmp_uc.qmsg
...\..\uc.amm.cdb
...\..\uc.asm.qmsg
...\..\uc.asm.rdb
...\..\uc.asm_labs.ddb
...\..\uc.cbx.xml
...\..\uc.cmp.bpm
...\..\uc.cmp.cdb
...\..\uc.cmp.hdb
...\..\uc.cmp.kpt
...\..\uc.cmp.logdb
...\..\uc.cmp.rdb
...\..\uc.cmp_merge.kpt
...\..\uc.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
...\..\uc.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd
...\..\uc.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
...\..\uc.db_info
...\..\uc.eda.qmsg
...\..\uc.fit.qmsg
...\..\uc.hier_info
...\..\uc.hif
...\..\uc.idb.cdb
...\..\uc.lpc.html
...\..\uc.lpc.rdb
...\..\uc.lpc.txt
...\..\uc.map.bpm
...\..\uc.map.cdb
...\..\uc.map.hdb
...\..\uc.map.kpt
...\..\uc.map.logdb
...\..\uc.map.qmsg
...\..\uc.map_bb.cdb
...\..\uc.map_bb.hdb
...\..\uc.map_bb.logdb
...\..\uc.pre_map.cdb
...\..\uc.pre_map.hdb
...\..\uc.rtlv.hdb
...\..\uc.rtlv_sg.cdb
...\..\uc.rtlv_sg_swap.cdb
...\..\uc.sgdiff.cdb
...\..\uc.sgdiff.hdb
...\..\uc.sld_design_entry.sci
...\..\uc.sld_design_entry_dsc.sci
...\..\uc.smart_action.txt
...\..\uc.smp_dump.txt
...\..\uc.sta.qmsg
...\..\uc.sta.rdb
...\..\uc.sta_cmp.8_slow_1200mv_85c.tdb
...\..\uc.syn_hier_info
...\..\uc.tiscmp.fastest_slow_1200mv_0c.ddb
...\..\uc.tiscmp.fastest_slow_1200mv_85c.ddb
...\..\uc.tiscmp.fast_1200mv_0c.ddb
...\..\uc.tiscmp.slow_1200mv_0c.ddb
...\..\uc.tiscmp.slow_1200mv_85c.ddb
...\..\uc.tis_db_list.ddb
...\Effect_Usb.v
...\Effect_Usb.v.bak
...\Effect_Usb1.bsf
...\Effect_Usb1.v
...\Effect_Usb1.v.bak
...\Effect_Usb2.bsf
...\Effect_Usb2.v
...\Effect_Usb2.v.bak
...\Flashing.bsf
...\Flashing.v
...\Flashing.v.bak
...\incremental_db\compiled_partitions\uc.db_info
...\..............\...................\uc.root_partition.cmp.cdb
...\..............\...................\uc.root_partition.cmp.dfp
...\..............\...................\uc.root_partition.cmp.hdb
...\..............\...................\uc.root_partition.cmp.kpt
...\..............\...................\uc.root_partition.cmp.logdb
...\..............\...................\uc.root_partition.cmp.rcfdb
...\..............\...................\uc.root_partition.map.cdb
...\..............\...................\uc.root_partition.map.dpi
...\..............\...................\uc.root_partition.map.hbdb.cdb
...\..............\...................\uc.root_partition.map.hbdb.hb_info
...\..............\...................\uc.root_partition.map.hbdb.hdb
...\..............\...................\uc.root_partition.map.hbdb.sig
...\..............\...................\uc.root_partition.map.hdb
...\..............\...................\uc.root_partition.map.kpt
...\..............\README
...\Read_Usb.bsf
...\Read_Usb.v
...\Read_Usb.v.bak
...\simulation\modelsim\msim_transcript
...\..........\........\Read_Usb.vt
...\..........\........\Read_Usb.vt.bak
...\..........\........\rtl_work\@effect_@usb1\verilog.prw
...\..........\........\........\.............\verilog.psm
...\..........\........\........\.............\_primary.dat
...\..........\........\........\.............\_primary.dbs
...\..........\........\........\.............\_primary.vhd
...\..........\........\........\............2\verilog.prw
...\..........\........\........\.............\verilog.psm
...\..........\........\........\.............\_primary.dat
...\..........\........\........\.............\_primary.dbs