文件名称:VGA1
介绍说明－－下载内容均来自于网络，请自行研究使用
基于ALTERA DE2 开发板开发的VGA外接屏Verilog显示程序。-ALTERA DE2 development board based on the development of Verilog VGA external screen display program.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
VGA1\altpll0.bsf
....\altpll0.ppf
....\altpll0.qip
....\altpll0.v
....\altpll0_bb.v
....\Block2.bdf
....\db\add_sub_lkc.tdf
....\..\add_sub_mkc.tdf
....\..\alt_u_div_a2f.tdf
....\..\alt_u_div_g2f.tdf
....\..\alt_u_div_mve.tdf
....\..\logic_util_heursitic.dat
....\..\lpm_divide_0dm.tdf
....\..\lpm_divide_d6m.tdf
....\..\lpm_divide_dem.tdf
....\..\lpm_divide_g6m.tdf
....\..\prev_cmp_VGA1.qmsg
....\..\sign_div_unsign_akh.tdf
....\..\sign_div_unsign_klh.tdf
....\..\sign_div_unsign_nlh.tdf
....\..\VGA1.ace_cmp.bpm
....\..\VGA1.ace_cmp.cdb
....\..\VGA1.ace_cmp.hdb
....\..\VGA1.amm.cdb
....\..\VGA1.asm.qmsg
....\..\VGA1.asm.rdb
....\..\VGA1.asm_labs.ddb
....\..\VGA1.cbx.xml
....\..\VGA1.cmp.bpm
....\..\VGA1.cmp.cdb
....\..\VGA1.cmp.hdb
....\..\VGA1.cmp.kpt
....\..\VGA1.cmp.logdb
....\..\VGA1.cmp.rdb
....\..\VGA1.cmp0.ddb
....\..\VGA1.cmp1.ddb
....\..\VGA1.cmp_merge.kpt
....\..\VGA1.db_info
....\..\VGA1.eco.cdb
....\..\VGA1.eda.qmsg
....\..\VGA1.eds_overflow
....\..\VGA1.fit.qmsg
....\..\VGA1.fnsim.hdb
....\..\VGA1.fnsim.qmsg
....\..\VGA1.hier_info
....\..\VGA1.hif
....\..\VGA1.idb.cdb
....\..\VGA1.lpc.html
....\..\VGA1.lpc.rdb
....\..\VGA1.lpc.txt
....\..\VGA1.map.bpm
....\..\VGA1.map.cdb
....\..\VGA1.map.hdb
....\..\VGA1.map.kpt
....\..\VGA1.map.logdb
....\..\VGA1.map.qmsg
....\..\VGA1.map.rdb
....\..\VGA1.map_bb.cdb
....\..\VGA1.map_bb.hdb
....\..\VGA1.map_bb.logdb
....\..\VGA1.pre_map.cdb
....\..\VGA1.pre_map.hdb
....\..\VGA1.root_partition.map.reg_db.cdb
....\..\VGA1.routing.rdb
....\..\VGA1.rpp.qmsg
....\..\VGA1.rtlv.hdb
....\..\VGA1.rtlv_sg.cdb
....\..\VGA1.rtlv_sg_swap.cdb
....\..\VGA1.sgate.rvd
....\..\VGA1.sgate_sm.rvd
....\..\VGA1.sgdiff.cdb
....\..\VGA1.sgdiff.hdb
....\..\VGA1.sim.hdb
....\..\VGA1.sim.qmsg
....\..\VGA1.sim.rdb
....\..\VGA1.sim.vwf
....\..\VGA1.simfam
....\..\VGA1.sld_design_entry.sci
....\..\VGA1.sld_design_entry_dsc.sci
....\..\VGA1.smart_action.txt
....\..\VGA1.sta.qmsg
....\..\VGA1.sta.rdb
....\..\VGA1.sta_cmp.6_slow.tdb
....\..\VGA1.syn_hier_info
....\..\VGA1.tis_db_list.ddb
....\..\VGA1.tmw_info
....\DE2_35_pin_assignments.csv
....\decimal2BCD.bsf
....\decimal2BCD.v
....\decimal2BCD.v.bak
....\greybox_tmp\cbx_args.txt
....\Hex_BCD.bsf
....\Hex_BCD.v
....\Hex_BCD1.v
....\incremental_db\compiled_partitions\VGA1.db_info
....\..............\...................\VGA1.root_partition.cmp.cdb
....\..............\...................\VGA1.root_partition.cmp.dfp
....\..............\...................\VGA1.root_partition.cmp.hdb
....\..............\...................\VGA1.root_partition.cmp.kpt
....\..............\...................\VGA1.root_partition.cmp.logdb