文件名称:verilog_stand_cell_lib
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verilog 门级设计及仿真标准单元库，包含142个基本的逻辑门单元。可用于VERILOG开发实现与或非、加法、减法、累加等基本的逻辑运算单元，实现精确的逻辑仿真。-verilog gate-level design and simulation of a standard cell library contains 142 basic logic gate unit. VERILOG implementation and can be used to develop or, addition, subtraction, accumulation, and other basic logic unit for accurate logic simulation
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下载文件列表
IC035os142_udp.v
IC035os142.v