文件名称:61EDA_C2212
- 所属分类：
- VHDL编程
- 资源属性：
- [Windows] [Visual C] [源码]
- 上传时间：
- 2013-05-30
- 文件大小：
- 3.42mb
- 下载次数：
- 0次
- 提 供 者：
- xue****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
红色飓风II开发板USB2FPGA USB驱动程序，由verilog编写，包括源码和FIFO测试程序-Red Hurricane II development board USB2FPGA USB driver from verilog preparation, including source code and test procedures FIFO
(系统自动生成,下载前可以参看下载内容)
下载文件列表
USB2.0接口的设计与实现\68013 slave fifo说明文档.doc
......................\写FIFO\写FIFO\Apptest\ezusbsys.h
......................\......\......\.......\ReadMe.txt
......................\......\......\.......\..lease\StdAfx.obj
......................\......\......\.......\.......\Test.exe
......................\......\......\.......\.......\Test.obj
......................\......\......\.......\.......\Test.res
......................\......\......\.......\.......\TestDlg.obj
......................\......\......\.......\.......\vc60.idb
......................\......\......\.......\res\cursor1.cur
......................\......\......\.......\...\icon5.ico
......................\......\......\.......\...\Test.ico
......................\......\......\.......\...\Test.rc2
......................\......\......\.......\...\usb.ico
......................\......\......\.......\Resource.h
......................\......\......\.......\StdAfx.cpp
......................\......\......\.......\StdAfx.h
......................\......\......\.......\Test.aps
......................\......\......\.......\Test.clw
......................\......\......\.......\Test.cpp
......................\......\......\.......\Test.dsp
......................\......\......\.......\Test.dsw
......................\......\......\.......\Test.h
......................\......\......\.......\Test.ncb
......................\......\......\.......\Test.opt
......................\......\......\.......\Test.plg
......................\......\......\.......\Test.rc
......................\......\......\.......\TestDlg.cpp
......................\......\......\.......\TestDlg.h
......................\......\......\wr_fifo\cmp_state.ini
......................\......\......\.......\db\cntr_l18.tdf
......................\......\......\.......\..\cntr_n28.tdf
......................\......\......\.......\..\wr_fifo.asm.qmsg
......................\......\......\.......\..\wr_fifo.cbx.xml
......................\......\......\.......\..\wr_fifo.cmp.cdb
......................\......\......\.......\..\wr_fifo.cmp.hdb
......................\......\......\.......\..\wr_fifo.cmp.rdb
......................\......\......\.......\..\wr_fifo.cmp.tdb
......................\......\......\.......\..\wr_fifo.cmp0.ddb
......................\......\......\.......\..\wr_fifo.db_info
......................\......\......\.......\..\wr_fifo.eco.cdb
......................\......\......\.......\..\wr_fifo.fit.qmsg
......................\......\......\.......\..\wr_fifo.hier_info
......................\......\......\.......\..\wr_fifo.hif
......................\......\......\.......\..\wr_fifo.map.cdb
......................\......\......\.......\..\wr_fifo.map.hdb
......................\......\......\.......\..\wr_fifo.map.qmsg
......................\......\......\.......\..\wr_fifo.pre_map.cdb
......................\......\......\.......\..\wr_fifo.pre_map.hdb
......................\......\......\.......\..\wr_fifo.psp
......................\......\......\.......\..\wr_fifo.rtlv.hdb
......................\......\......\.......\..\wr_fifo.rtlv_sg.cdb
......................\......\......\.......\..\wr_fifo.rtlv_sg_swap.cdb
......................\......\......\.......\..\wr_fifo.sgdiff.cdb
......................\......\......\.......\..\wr_fifo.sgdiff.hdb
......................\......\......\.......\..\wr_fifo.signalprobe.cdb
......................\......\......\.......\..\wr_fifo.sld_design_entry.sci
......................\......\......\.......\..\wr_fifo.sld_design_entry_dsc.sci
......................\......\......\.......\..\wr_fifo.smp_dump.txt
......................\......\......\.......\..\wr_fifo.syn_hier_info
......................\......\......\.......\..\wr_fifo.tan.qmsg
......................\......\......\.......\..\wr_fifo_cmp.qrpt
......................\......\......\.......\transcript
......................\......\......\.......\vish_stacktrace.vstf
......................\......\......\.......\vsim.wlf
......................\......\......\.......\work\wr_fifo\verilog.asm
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