文件名称:Odd-Frequence-Dividing-Circuit
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一种奇数分频电路的设计方法,采用verilog HDL描述。修改代码中参数可以进行任意奇数分频,包含了设计文档和源代码。-A design of odd frequence dividing circuit is presented, which is described by verilog HDL。Change the parameter in code, one can get any odd numbers of frequence dividing circuit.
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下载文件列表
Odd Frequence Dividing Circuit\5fenpin\clk_div5.cr.mti
..............................\.......\clk_div5.mpf
..............................\.......\clk_div5.v
..............................\.......\clk_div5.v.bak
..............................\.......\clk_div5_tb.v
..............................\.......\clk_div5_tb.v.bak
..............................\.......\top_uart_spread_modelsim.tcl
..............................\.......\vsim.wlf
..............................\.......\work\@_opt\vopt3x2shj
..............................\.......\....\.....\vopt7drnhj
..............................\.......\....\.....\voptadij1i
..............................\.......\....\.....\voptex7f1i
..............................\.......\....\.....\voptixrchj
..............................\.......\....\.....\voptmch62i
..............................\.......\....\.....\voptmde9hj
..............................\.......\....\.....\voptrw632i
..............................\.......\....\.....\voptsx36hj
..............................\.......\....\.....\voptwcw02i
..............................\.......\....\.....\voptwds2hj
..............................\.......\....\.....\_deps
..............................\.......\....\.....1\vopt2810ja
..............................\.......\....\......\vopt4k0a4b
..............................\.......\....\......\vopt5rnxia
..............................\.......\....\......\vopt84n74b
..............................\.......\....\......\vopt9rgt29
..............................\.......\....\......\voptbkb44b
..............................\.......\....\......\voptcrani7
..............................\.......\....\......\voptf4104b
..............................\.......\....\......\voptg56jj5
..............................\.......\....\......\voptjknx3b
..............................\.......\....\......\voptn4ct3b
..............................\.......\....\......\voptt7n7ja
..............................\.......\....\......\voptyqb4ja
..............................\.......\....\......\_deps
..............................\.......\....\clk_div5\_primary.dat
..............................\.......\....\........\_primary.dbs
..............................\.......\....\........\_primary.vhd
..............................\.......\....\........_tb\_primary.dat
..............................\.......\....\...........\_primary.dbs
..............................\.......\....\...........\_primary.vhd
..............................\.......\....\div_five\verilog.asm
..............................\.......\....\........\verilog.rw
..............................\.......\....\........\_primary.dat
..............................\.......\....\........\_primary.dbs
..............................\.......\....\........\_primary.vhd
..............................\.......\....\test_div_five\verilog.asm
..............................\.......\....\.............\verilog.rw
..............................\.......\....\.............\_primary.dat
..............................\.......\....\.............\_primary.dbs
..............................\.......\....\.............\_primary.vhd
..............................\.......\....\_info
..............................\.......\....\.temp\vlog2yd23e
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