文件名称:24CIC
- 所属分类：
- VHDL编程
- 资源属性：
- [Matlab] [源码]
- 上传时间：
- 2013-05-25
- 文件大小：
- 3.47mb
- 下载次数：
- 0次
- 提 供 者：
- zengd*****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
基于fpga的抽取CIC滤波器设计,采用verilog编写，24抽取,仿真通过-Fpga-based CIC decimation filter design using verilog written, 24 extraction
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下载文件列表
高级篇01：4阶24倍抽取CIC滤波器设计\scr\cic_dec24.v
..................................\...\cic_dec_arithmetic.v
..................................\...\cic_filter_32add.v
..................................\...\derivative_filter.v
..................................\...\der_filter_27sub.v
..................................\...\der_filter_dpram.v
..................................\...\iqdata_24dec_adpram.v
..................................\...\monopole_integrator_first.v
..................................\...\multilevel_der_filter.v
..................................\...\multilevel_integrator.v
..................................\...\signal_gen0.v
..................................\...\signal_gen1.v
..................................\...\tb_cic.v
..................................\.im\fft_analyz_out.asv
..................................\...\fft_analyz_out.m
..................................\...\fft_analyz_signal.m
..................................\...\out_data.dat
..................................\...\signal_1m.dat
..................................\...\signal_data.dat
..................................\...\vsim.wlf
..................................\...\wave.do
..................................\...\wlftaeh4c2
..................................\...\.ork\cic_dec24\verilog.asm
..................................\...\....\.........\verilog.rw
..................................\...\....\.........\_primary.dat
..................................\...\....\.........\_primary.dbs
..................................\...\....\.........\_primary.vhd
..................................\...\....\......._arithmetic\verilog.asm
..................................\...\....\..................\verilog.rw
..................................\...\....\..................\_primary.dat
..................................\...\....\..................\_primary.dbs
..................................\...\....\..................\_primary.vhd
..................................\...\....\derivative_filter\verilog.asm
..................................\...\....\.................\verilog.rw
..................................\...\....\.................\_primary.dat
..................................\...\....\.................\_primary.dbs
..................................\...\....\.................\_primary.vhd
..................................\...\....\..._filter_27sub\verilog.asm
..................................\...\....\................\verilog.rw
..................................\...\....\................\_primary.dat
..................................\...\....\................\_primary.dbs
..................................\...\....\................\_primary.vhd
..................................\...\....\monopole_integrator_first\verilog.asm
..................................\...\....\.........................\verilog.rw
..................................\...\....\.........................\_primary.dat
..................................\...\....\.........................\_primary.dbs
..................................\...\....\.........................\_primary.vhd
..................................\...\....\.ultilevel_der_filter\verilog.asm
..................................\...\....\.....................\verilog.rw
..................................\...\....\.....................\_primary.dat
..................................\...\....\.....................\_primary.dbs
..................................\...\....\.....................\_primary.vhd
..................................\...\....\...........integrator\verilog.asm
..................................\...\....\.....................\verilog.rw
..................................\...\....\.....................\_primary.dat
..................................\...\....\.....................\_primary.dbs
..................................\...\....\.....................\_primary.vhd
..................................\...\....\signal_gen0\verilog.asm
..................................\...\....\...........\verilog.rw
..................................\...\....\...........\_primary.dat
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