文件名称:cputest
介绍说明－－下载内容均来自于网络，请自行研究使用
通过verilog语言设计的简单CPU，可完成加减乘除和算数逻辑移位功能。-By verilog language design simple CPU, to be completed by addition, subtraction, and arithmetic logic shift function.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
04010102cpu\CPU\1-100.vwf
...........\...\2-10.hex
...........\...\2-100.vwf
...........\...\ACC.bsf
...........\...\ACC.vhd
...........\...\ACC.vhd.bak
...........\...\ALU.bsf
...........\...\ALU.vhd
...........\...\ALU.vhd.bak
...........\...\BR.bsf
...........\...\BR.vhd
...........\...\BR.vhd.bak
...........\...\Control_Unit.bsf
...........\...\Control_Unit.vhd
...........\...\Control_Unit.vhd.bak
...........\...\CPU.asm.rpt
...........\...\CPU.bdf
...........\...\CPU.done
...........\...\CPU.fit.rpt
...........\...\CPU.fit.smsg
...........\...\CPU.fit.summary
...........\...\CPU.flow.rpt
...........\...\CPU.map.rpt
...........\...\CPU.map.summary
...........\...\CPU.pin
...........\...\CPU.pof
...........\...\CPU.qpf
...........\...\CPU.qsf
...........\...\CPU.qws
...........\...\CPU.sim.rpt
...........\...\CPU.sof
...........\...\CPU.tan.rpt
...........\...\CPU.tan.summary
...........\...\CPU.vcd
...........\...\CPU_Exam.mif
...........\...\CPU_Exam.mif.bak
...........\...\CPU_Exam.vwf
...........\...\CPU_Test.vwf
...........\...\CPU_Test_Functional.vwf
...........\...\db\altsyncram_7rd1.tdf
...........\...\..\altsyncram_8ic1.tdf
...........\...\..\altsyncram_a3v.tdf
...........\...\..\altsyncram_boe1.tdf
...........\...\..\altsyncram_grd1.tdf
...........\...\..\altsyncram_h6d1.tdf
...........\...\..\altsyncram_idd1.tdf
...........\...\..\altsyncram_isc1.tdf
...........\...\..\altsyncram_mae1.tdf
...........\...\..\altsyncram_rvd1.tdf
...........\...\..\alt_u_div_u6f.tdf
...........\...\..\CPU.asm.qmsg
...........\...\..\CPU.asm_labs.ddb
...........\...\..\CPU.cbx.xml
...........\...\..\CPU.cmp.bpm
...........\...\..\CPU.cmp.cdb
...........\...\..\CPU.cmp.ecobp
...........\...\..\CPU.cmp.hdb
...........\...\..\CPU.cmp.logdb
...........\...\..\CPU.cmp.rdb
...........\...\..\CPU.cmp.tdb
...........\...\..\CPU.cmp0.ddb
...........\...\..\CPU.cmp_bb.cdb
...........\...\..\CPU.cmp_bb.hdb
...........\...\..\CPU.cmp_bb.logdb
...........\...\..\CPU.cmp_bb.rcf
...........\...\..\CPU.dbp
...........\...\..\CPU.db_info
...........\...\..\CPU.eco.cdb
...........\...\..\CPU.eds_overflow
...........\...\..\CPU.fit.qmsg
...........\...\..\CPU.fnsim.cdb
...........\...\..\CPU.fnsim.hdb
...........\...\..\CPU.fnsim.qmsg
...........\...\..\CPU.hier_info
...........\...\..\CPU.hif
...........\...\..\CPU.map.bpm
...........\...\..\CPU.map.cdb
...........\...\..\CPU.map.ecobp
...........\...\..\CPU.map.hdb
...........\...\..\CPU.map.logdb
...........\...\..\CPU.map.qmsg
...........\...\..\CPU.map_bb.cdb
...........\...\..\CPU.map_bb.hdb
...........\...\..\CPU.map_bb.logdb
...........\...\..\CPU.pre_map.cdb
...........\...\..\CPU.pre_map.hdb
...........\...\..\CPU.psp
...........\...\..\CPU.pss
...........\...\..\CPU.rtlv.hdb
...........\...\..\CPU.rtlv_sg.cdb
...........\...\..\CPU.rtlv_sg_swap.cdb
...........\...\..\CPU.sgdiff.cdb
...........\...\..\CPU.sgdiff.hdb
...........\...\..\CPU.signalprobe.cdb
...........\...\..\CPU.sim.cvwf
...........\...\..\CPU.sim.hdb
...........\...\..\CPU.sim.qmsg
...........\...\..\CPU.sim.rdb
...........\...\..\CPU.sld_design_entry.sci
...........\...\..\CPU.sld_design_entry_dsc.sci