文件名称:Nios_ii_8.0_back
介绍说明--下载内容均来自于网络,请自行研究使用
altera FPGA nios 实例,实现网络通信。-altera FPGA nios example, network communications.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Nios_ii_8.0_back\.sopc_builder\filters.xml
................\.............\install.ptf
................\.............\install2.ptf
................\.............\preferences.xml
................\altpllpll_0.bsf
................\altpllpll_0.ppf
................\altpllpll_0.qip
................\altpllpll_0.v
................\altpllpll_0_bb.v
................\altpllpll_0_wave0.jpg
................\altpllpll_0_waveforms.html
................\altpllsys_pll.cmp
................\altpllsys_pll.ppf
................\altpllsys_pll.qip
................\altpllsys_pll.v
................\altpllsys_pll_bb.v
................\altpllsys_pll_wave0.jpg
................\altpllsys_pll_waveforms.html
................\altplltse_pll.bsf
................\altplltse_pll.ppf
................\altplltse_pll.qip
................\altplltse_pll.v
................\altplltse_pll_bb.v
................\altplltse_pll_wave0.jpg
................\altplltse_pll_waveforms.html
................\button_no_shake.bsf
................\button_no_shake.cmp
................\button_no_shake.inc
................\button_no_shake.v
................\button_no_shake_inst.v
................\cpu.ocp
................\cpu.sdc
................\cpu.v
................\cpu_0.ocp
................\cpu_0.sdc
................\cpu_0.v
................\cpu_0_jtag_debug_module_sysclk.v
................\cpu_0_jtag_debug_module_tck.v
................\cpu_0_jtag_debug_module_wrapper.v
................\cpu_0_ociram_default_contents.mif
................\cpu_0_oci_test_bench.v
................\cpu_0_rf_ram.mif
................\cpu_0_test_bench.v
................\cpu_bht_ram.mif
................\cpu_ic_tag_ram.mif
................\cpu_jtag_debug_module_sysclk.v
................\cpu_jtag_debug_module_tck.v
................\cpu_jtag_debug_module_wrapper.v
................\cpu_mult_cell.v
................\cpu_ociram_default_contents.mif
................\cpu_oci_test_bench.v
................\cpu_rf_ram_a.mif
................\cpu_rf_ram_b.mif
................\cpu_test_bench.v
................\data_port_hw.tcl
................\data_port_hw.tcl~
................\.b\add_sub_p2e.tdf
................\..\altpll_cod1.tdf
................\..\altsyncram_0j91.tdf
................\..\altsyncram_15g1.tdf
................\..\altsyncram_18g1.tdf
................\..\altsyncram_1j22.tdf
................\..\altsyncram_26f1.tdf
................\..\altsyncram_2of1.tdf
................\..\altsyncram_36f1.tdf
................\..\altsyncram_3eg1.tdf
................\..\altsyncram_4fc1.tdf
................\..\altsyncram_6472.tdf
................\..\altsyncram_78g1.tdf
................\..\altsyncram_deg1.tdf
................\..\altsyncram_ef41.tdf
................\..\altsyncram_f0b1.tdf
................\..\altsyncram_f4g1.tdf
................\..\altsyncram_i0m1.tdf
................\..\altsyncram_j0b1.tdf
................\..\altsyncram_jid1.tdf
................\..\altsyncram_k8a1.tdf
................\..\altsyncram_lta1.tdf
................\..\altsyncram_n802.tdf
................\..\altsyncram_o761.tdf
................\..\altsyncram_qsd1.tdf
................\..\altsyncram_spd1.tdf
................\..\altsyncram_utd1.tdf
................\..\a_dpfifo_3541.tdf
................\..\a_dpfifo_9i31.tdf
................\..\a_dpfifo_h031.tdf
................\..\a_dpfifo_qg31.tdf
................\..\a_fefifo_7cf.tdf
................\..\cmpr_tdg.tdf
................\..\cntr_4n7.tdf
................\..\cntr_g7h.tdf
................\..\cntr_hpf.tdf
................\..\cntr_i7h.tdf
................\..\cntr_jmb.tdf
................\..\cntr_n9f.tdf
................\..\cntr_nmb.tdf
................\..\cntr_omb.tdf
................\..\cntr_rnf.tdf
................\..\cntr_tnf.tdf
................\..\cntr_vm7.tdf