文件名称:dc_rmv
介绍说明－－下载内容均来自于网络，请自行研究使用
这是一个用verilog写的DC滤波器，即melp算法中预处理部分，主要滤除50hz工频干扰，采用一个4阶的切比雪夫高通滤波器，截去频率位60hz以下的信号，其阻带的衰减位30db。-This is a verilog to write a DC filter the preprocessing part that melp algorithm, main filter 50hz frequency interference, the use of a fourth-order Chebyshev high-pass filter, the truncated frequency bit 60hz signal, its resistance with attenuation bit 30dB.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
dc_rmv\1.cr.mti
......\1.mpf
......\220model.v
......\altera_mf.v
......\altera_primitives.v
......\db\dc_rmv.asm.qmsg
......\..\dc_rmv.asm_labs.ddb
......\..\dc_rmv.cbx.xml
......\..\dc_rmv.cmp.bpm
......\..\dc_rmv.cmp.cdb
......\..\dc_rmv.cmp.ecobp
......\..\dc_rmv.cmp.hdb
......\..\dc_rmv.cmp.logdb
......\..\dc_rmv.cmp.rdb
......\..\dc_rmv.cmp.tdb
......\..\dc_rmv.cmp0.ddb
......\..\dc_rmv.cmp_bb.cdb
......\..\dc_rmv.cmp_bb.hdb
......\..\dc_rmv.cmp_bb.logdb
......\..\dc_rmv.cmp_bb.rcf
......\..\dc_rmv.dbp
......\..\dc_rmv.db_info
......\..\dc_rmv.eco.cdb
......\..\dc_rmv.fit.qmsg
......\..\dc_rmv.hier_info
......\..\dc_rmv.hif
......\..\dc_rmv.map.bpm
......\..\dc_rmv.map.cdb
......\..\dc_rmv.map.ecobp
......\..\dc_rmv.map.hdb
......\..\dc_rmv.map.logdb
......\..\dc_rmv.map.qmsg
......\..\dc_rmv.map_bb.cdb
......\..\dc_rmv.map_bb.hdb
......\..\dc_rmv.map_bb.logdb
......\..\dc_rmv.pre_map.cdb
......\..\dc_rmv.pre_map.hdb
......\..\dc_rmv.psp
......\..\dc_rmv.pss
......\..\dc_rmv.rpp.qmsg
......\..\dc_rmv.rtlv.hdb
......\..\dc_rmv.rtlv_sg.cdb
......\..\dc_rmv.rtlv_sg_swap.cdb
......\..\dc_rmv.sgate.rvd
......\..\dc_rmv.sgate_sm.rvd
......\..\dc_rmv.sgdiff.cdb
......\..\dc_rmv.sgdiff.hdb
......\..\dc_rmv.signalprobe.cdb
......\..\dc_rmv.sld_design_entry.sci
......\..\dc_rmv.sld_design_entry_dsc.sci
......\..\dc_rmv.syn_hier_info
......\..\dc_rmv.tan.qmsg
......\..\dc_rmv.tis_db_list.ddb
......\..\mult_hoq.tdf
......\..\prev_cmp_dc_rmv.asm.qmsg
......\..\prev_cmp_dc_rmv.fit.qmsg
......\..\prev_cmp_dc_rmv.map.qmsg
......\..\prev_cmp_dc_rmv.qmsg
......\..\prev_cmp_dc_rmv.tan.qmsg
......\dc_input.dat
......\dc_rmv.asm.rpt
......\dc_rmv.bsf
......\dc_rmv.done
......\dc_rmv.dpf
......\dc_rmv.fit.rpt
......\dc_rmv.fit.smsg
......\dc_rmv.fit.summary
......\dc_rmv.flow.rpt
......\dc_rmv.map.rpt
......\dc_rmv.map.summary
......\dc_rmv.pin
......\dc_rmv.pof
......\dc_rmv.qpf
......\dc_rmv.qsf
......\dc_rmv.sof
......\dc_rmv.tan.rpt
......\dc_rmv.tan.summary
......\dc_rmv.v
......\dc_rmv.v.bak
......\dc_rmv_sim.v
......\Define_file.v
......\mult16_16.v
......\mult_add.v
......\ram_16_512.v
......\transcript
......\vsim.wlf
......\wave.do
......\.ork\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm
......\....\..........................................\verilog.rw
......\....\..........................................\_primary.dat
......\....\..........................................\_primary.dbs
......\....\..........................................\_primary.vhd
......\....\..............m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n\_primary.dat
......\....\...............................................\_primary.dbs
......\....\...............................................\_primary.vhd
......\....\...................m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n\verilog.asm
......\....\...........................................................\verilog.rw
......\....\...........................................................\_primary.dat
......\....\...........................................................\_primary.dbs
......\....\...........................................................\_primary.vhd