文件名称:Digital_Clock
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FPGA数字时钟完美通过测试。目标板是ZRTECH的EP2C5T144C8 CORE2-5U核心板及PERI1-8KD配套子卡。-The FPGA digital clock perfect pass the test. The target board is ZRTECH EP2C5T144C8 CORE2-5U core board and PERI1-8KD supporting daughter card.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
clock_test\clk_1Hz.v
..........\clk_1Hz.v.bak
..........\clk_1Hz.qpf
..........\clk_1Hz.qsf
..........\clk_1Hz.map.summary
..........\clk_1Hz.flow.rpt
..........\clk_1Hz.tan.rpt
..........\clk_1Hz.pin
..........\clk_1Hz.fit.smsg
..........\clk_1Hz.fit.summary
..........\clk_1Hz.cdf
..........\clk_1Hz.map.rpt
..........\shift8.v
..........\clk_1Hz.sof
..........\clk_1Hz.pof
..........\clk_1Hz.fit.rpt
..........\clk_1Hz.asm.rpt
..........\clk_1Hz.tan.summary
..........\shift8.v.bak
..........\sec.v
..........\sec.v.bak
..........\sec.bsf
..........\clk_1Hz.done
..........\clk_1Hz.bsf
..........\clk_1Hz.dpf
..........\min.v
..........\min.bsf
..........\shift8.bsf
..........\hour.v
..........\CORE2-5U-SLOT1.tcl
..........\min.v.bak
..........\hour.bsf
..........\seltimev.v
..........\SELTIMEV.bsf
..........\decodev.v
..........\SELTIMEv_zh.v
..........\DECODEV.bsf
..........\SELTIMEv_zh.v.bak
..........\decodev.v.bak
..........\clk_half.v
..........\clk_half.bsf
..........\简易数字钟BDF文件.pdf
..........\hour.v.bak
..........\clk_1Hz.qws
..........\Block1.bdf
..........\clk_1Hz.map.smsg
..........\incremental_db\README
..........\..............\compiled_partitions\clk_1Hz.root_partition.cmp.dfp
..........\..............\...................\clk_1Hz.root_partition.map.kpt
..........\..............\...................\clk_1Hz.root_partition.cmp.rcfdb
..........\..............\...................\clk_1Hz.root_partition.cmp.cdb
..........\..............\...................\clk_1Hz.root_partition.cmp.hdb
..........\..............\...................\clk_1Hz.root_partition.map.dpi
..........\..............\...................\clk_1Hz.root_partition.cmp.re.rcfdb
..........\..............\...................\clk_1Hz.root_partition.cmp.logdb
..........\..............\...................\clk_1Hz.root_partition.cmp.kpt
..........\..............\...................\clk_1Hz.root_partition.map.cdb
..........\..............\...................\clk_1Hz.root_partition.map.hdb
..........\db\prev_cmp_clk_1Hz.qmsg
..........\..\clk_1Hz.db_info
..........\..\clk_1Hz.map.qmsg
..........\..\prev_cmp_clk_1Hz.map.qmsg
..........\..\clk_1Hz.cmp.cdb
..........\..\prev_cmp_clk_1Hz.fit.qmsg
..........\..\prev_cmp_clk_1Hz.asm.qmsg
..........\..\logic_util_heursitic.dat
..........\..\prev_cmp_clk_1Hz.tan.qmsg
..........\..\clk_1Hz.cbx.xml
..........\..\clk_1Hz.hif
..........\..\clk_1Hz.hier_info
..........\..\clk_1Hz.rtlv_sg_swap.cdb
..........\..\clk_1Hz.smart_action.txt
..........\..\clk_1Hz.lpc.txt
..........\..\clk_1Hz.tis_db_list.ddb
..........\..\clk_1Hz.lpc.html
..........\..\clk_1Hz.fit.qmsg
..........\..\clk_1Hz.cmp.logdb
..........\..\clk_1Hz.asm.qmsg
..........\..\clk_1Hz.pre_map.cdb
..........\..\clk_1Hz.tan.qmsg
..........\..\clk_1Hz.pre_map.hdb
..........\..\clk_1Hz.syn_hier_info
..........\..\clk_1Hz.map.ecobp
..........\..\clk_1Hz.map.kpt
..........\..\clk_1Hz.cmp_merge.kpt
..........\..\clk_1Hz.cmp2.ddb
..........\..\clk_1Hz.map_bb.logdb
..........\..\clk_1Hz.sld_design_entry.sci
..........\..\clk_1Hz.sgdiff.cdb
..........\..\clk_1Hz.cmp.kpt
..........\..\clk_1Hz.cmp.ecobp
..........\..\clk_1Hz.rtlv_sg.cdb
..........\..\clk_1Hz.lpc.rdb
..........\..\clk_1Hz.rtlv.hdb
..........\..\clk_1Hz.sgdiff.hdb
..........\..\clk_1Hz.sld_design_entry_dsc.sci
..........\..\clk_1Hz.cmp.bpm
..........\..\clk_1Hz.map_bb.cdb
..........\..\clk_1Hz.map.cdb
..........\..\clk_1Hz.map_bb.hdb