文件名称:signal-generator
介绍说明－－下载内容均来自于网络，请自行研究使用
Design of DDS signal generator based on VHDL+FPGA, has been through the adjustable, can be directly used, simulation
-DDS signal generator circuit design, Verilog source code, can be directly used, simulation
-DDS signal generator circuit design, Verilog source code, can be directly used, simulation
(系统自动生成,下载前可以参看下载内容)
下载文件列表
DDS信号发生器\db\add_sub_1rh.tdf
.............\..\add_sub_2rh.tdf
.............\..\add_sub_4rh.tdf
.............\..\add_sub_5rh.tdf
.............\..\add_sub_8rh.tdf
.............\..\add_sub_jsh.tdf
.............\..\add_sub_ksh.tdf
.............\..\add_sub_nsh.tdf
.............\..\altsyncram_0to3.tdf
.............\..\altsyncram_5931.tdf
.............\..\altsyncram_hc31.tdf
.............\..\altsyncram_i931.tdf
.............\..\altsyncram_jd31.tdf
.............\..\cmpr_j4c.tdf
.............\..\cmpr_n4c.tdf
.............\..\cntr_c4i.tdf
.............\..\cntr_iti.tdf
.............\..\cntr_r2i.tdf
.............\..\cntr_umi.tdf
.............\..\DDS_1.asm.qmsg
.............\..\DDS_1.cbx.xml
.............\..\DDS_1.cmp.bpm
.............\..\DDS_1.cmp.cdb
.............\..\DDS_1.cmp.ecobp
.............\..\DDS_1.cmp.hdb
.............\..\DDS_1.cmp.kpt
.............\..\DDS_1.cmp.logdb
.............\..\DDS_1.cmp.rdb
.............\..\DDS_1.cmp.tdb
.............\..\DDS_1.cmp0.ddb
.............\..\DDS_1.cmp_merge.kpt
.............\..\DDS_1.db_info
.............\..\DDS_1.eco.cdb
.............\..\DDS_1.eds_overflow
.............\..\DDS_1.fit.qmsg
.............\..\DDS_1.fnsim.cdb
.............\..\DDS_1.fnsim.hdb
.............\..\DDS_1.fnsim.qmsg
.............\..\DDS_1.hier_info
.............\..\DDS_1.hif
.............\..\DDS_1.lpc.html
.............\..\DDS_1.lpc.rdb
.............\..\DDS_1.lpc.txt
.............\..\DDS_1.map.bpm
.............\..\DDS_1.map.cdb
.............\..\DDS_1.map.ecobp
.............\..\DDS_1.map.hdb
.............\..\DDS_1.map.kpt
.............\..\DDS_1.map.logdb
.............\..\DDS_1.map.qmsg
.............\..\DDS_1.map_bb.cdb
.............\..\DDS_1.map_bb.hdb
.............\..\DDS_1.map_bb.logdb
.............\..\DDS_1.pre_map.cdb
.............\..\DDS_1.pre_map.hdb
.............\..\DDS_1.rtlv.hdb
.............\..\DDS_1.rtlv_sg.cdb
.............\..\DDS_1.rtlv_sg_swap.cdb
.............\..\DDS_1.sgdiff.cdb
.............\..\DDS_1.sgdiff.hdb
.............\..\DDS_1.sim.cvwf
.............\..\DDS_1.sim.hdb
.............\..\DDS_1.sim.qmsg
.............\..\DDS_1.sim.rdb
.............\..\DDS_1.simfam
.............\..\DDS_1.sld_design_entry.sci
.............\..\DDS_1.sld_design_entry_dsc.sci
.............\..\DDS_1.syn_hier_info
.............\..\DDS_1.tan.qmsg
.............\..\DDS_1.tis_db_list.ddb
.............\..\DDS_1_global_asgn_op.abo
.............\..\decode_9jf.tdf
.............\..\mux_6hc.tdf
.............\..\mux_oic.tdf
.............\..\mux_pgc.tdf
.............\..\prev_cmp_DDS_1.qmsg
.............\..\wed.wsf
.............\DDS.bsf
.............\DDS.v
.............\DDS_1.asm.rpt
.............\DDS_1.done
.............\DDS_1.dpf
.............\DDS_1.fit.rpt
.............\DDS_1.fit.smsg
.............\DDS_1.fit.summary
.............\DDS_1.flow.rpt
.............\DDS_1.jdi
.............\DDS_1.map.rpt
.............\DDS_1.map.smsg
.............\DDS_1.map.summary
.............\DDS_1.pin
.............\DDS_1.pof
.............\DDS_1.qpf
.............\DDS_1.qsf
.............\DDS_1.qws
.............\DDS_1.sim.rpt
.............\DDS_1.sof
.............\DDS_1.tan.rpt
.............\DDS_1.tan.summary
.............\DDS_1.vwf