文件名称:i2c-verilog-vhdl
- 所属分类:
- Internet/网络编程
- 资源属性:
- [PDF]
- 上传时间:
- 2013-05-15
- 文件大小:
- 663kb
- 下载次数:
- 0次
- 提 供 者:
- xum***
- 相关连接:
- 无
- 下载说明:
- 别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容均来自于网络,请自行研究使用
I2C总线VHDL/Verilog HDL源码
通过仿真验证正确,希望对大家有用-I2C bus VHDL/Verilog HDL source code is verified by simulation is correct, we hope to useful
通过仿真验证正确,希望对大家有用-I2C bus VHDL/Verilog HDL source code is verified by simulation is correct, we hope to useful
(系统自动生成,下载前可以参看下载内容)
下载文件列表
i2c verilog vhdl
................\CVS
................\...\Entries
................\...\Repository
................\...\Root
................\bench
................\.....\CVS
................\.....\...\Entries
................\.....\...\Repository
................\.....\...\Root
................\.....\verilog
................\.....\.......\CVS
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................\.....\.......\...\Root
................\.....\.......\i2c_slave_model.v
................\.....\.......\spi_slave_model.v
................\.....\.......\tst_bench_top.v
................\.....\.......\wb_master_model.v
................\doc
................\...\CVS
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................\...\...\Repository
................\...\...\Root
................\...\i2c_specs.pdf
................\...\src
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................\...\...\I2C_specs.doc
................\documentation
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................\rtl
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................\...\...\Repository
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................\...\verilog
................\...\.......\CVS
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................\...\.......\i2c_master_bit_ctrl.v
................\...\.......\i2c_master_byte_ctrl.v
................\...\.......\i2c_master_defines.v
................\...\.......\i2c_master_top.v
................\...\.......\timescale.v
................\...\vhdl
................\...\....\CVS
................\...\....\...\Entries
................\...\....\...\Repository
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................\...\....\I2C.VHD
................\...\....\i2c_master_bit_ctrl.vhd
................\...\....\i2c_master_byte_ctrl.vhd
................\...\....\i2c_master_top.vhd
................\...\....\readme
................\...\....\tst_ds1621.vhd
................\sim
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................\...\...........\run
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................\...\...........\...\INCA_libs
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................\...\...........\...\bench.vcd
................\...\...........\...\ncverilog.key
................\...\...........\...\ncverilog.log
................\...\...........\...\run
................\...\...........\...\waves
................\...\...........\...\.....\CVS
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................\software
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................\........\drivers
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