VHDL做的电子钟\dianzizhong\1111\count10.vhd

..............\...........\....\choi6_1.vhd

..............\...........\....\weixuan.vhd

..............\...........\....\bcd0.vhd

..............\...........\....\fenpingqi.vhd

..............\...........\....\dzz.vhd

..............\...........\dzz.qpf

..............\...........\dzz.qsf

..............\...........\.b\dzz.psp

..............\...........\..\dzz.db_info

..............\...........\..\dzz.map.qmsg

..............\...........\..\dzz.sld_design_entry.sci

..............\...........\..\dzz.cmp.rdb

..............\...........\..\dzz.hier_info

..............\...........\..\dzz.eco.cdb

..............\...........\..\dzz.cbx.xml

..............\...........\..\dzz.syn_hier_info

..............\...........\..\mux_jcc.tdf

..............\...........\..\dzz.fit.qmsg

..............\...........\..\dzz.rtlv.hdb

..............\...........\..\dzz.pre_map.cdb

..............\...........\..\dzz.map.logdb

..............\...........\..\dzz.map.cdb

..............\...........\..\dzz.hif

..............\...........\..\dzz.sim.qmsg

..............\...........\..\dzz.sim.vwf

..............\...........\..\mux_3ec.tdf

..............\...........\..\dzz.dbp

..............\...........\..\dzz.rtlv_sg.cdb

..............\...........\..\wed.zsf

..............\...........\..\dzz.sgdiff.hdb

..............\...........\..\dzz.rpp.qmsg

..............\...........\..\dzz.fnsim.qmsg

..............\...........\..\dzz.cmp.logdb

..............\...........\..\dzz.cmp.kpt

..............\...........\..\dzz.sgate.rvd

..............\...........\..\dzz.map.hdb

..............\...........\..\dzz.asm.qmsg

..............\...........\..\dzz.tan.qmsg

..............\...........\..\dzz.sgate_sm.rvd

..............\...........\..\dzz.rtlv_sg_swap.cdb

..............\...........\..\dzz.pre_map.hdb

..............\...........\..\dzz.sgdiff.cdb

..............\...........\..\dzz.sim.rdb

..............\...........\..\dzz.cmp0.ddb

..............\...........\..\add_sub_3rh.tdf

..............\...........\..\add_sub_5rh.tdf

..............\...........\..\add_sub_2rh.tdf

..............\...........\..\add_sub_4rh.tdf

..............\...........\..\dzz.eds_overflow

..............\...........\..\dzz.cmp.cdb

..............\...........\..\dzz.fnsim.hdb

..............\...........\..\dzz.sim.hdb

..............\...........\..\dzz.signalprobe.cdb

..............\...........\..\dzz.cmp.hdb

..............\...........\..\dzz.cmp.tdb

..............\...........\..\dzz.fnsim.cdb

..............\...........\..\dzz.sld_design_entry_dsc.sci

..............\...........\dzz.vhd

..............\...........\dzz.map.rpt

..............\...........\dzz.flow.rpt

..............\...........\dzz.map.summary

..............\...........\dzz.qws

..............\...........\dzz.pin

..............\...........\dzz.fit.rpt

..............\...........\dzz.fit.smsg

..............\...........\dzz.fit.summary

..............\...........\dzz.sof

..............\...........\dzz.pof

..............\...........\dzz.asm.rpt

..............\...........\dzz.tan.summary

..............\...........\dzz.tan.rpt

..............\...........\dzz.done

..............\...........\dzz.sim.rpt

..............\...........\dzz.vwf

..............\CPLD专题实习－2011-2012(1).ppt

..............\dianzizhong\1111

..............\...........\db

..............\dianzizhong

VHDL做的电子钟