最全的FPGA VGA方面的资料及源码\最全的FPGA VGA方面的资料及源码\vga\VGA IPcore的Verilog代码\VGA IPcore的Verilog代码\VGALCD\b13_safe_09_17_02\auto_baud.v

..............................\..............................\...\.......................\.......................\......\.................\auto_baud_with_tracking.v

..............................\..............................\...\.......................\.......................\......\.................\build_13.ucf

..............................\..............................\...\.......................\.......................\......\.................\clock_divider.v

..............................\..............................\...\.......................\.......................\......\.................\clock_multiply.v

..............................\..............................\...\.......................\.......................\......\.................\reg_4_pack_clrset.v

..............................\..............................\...\.......................\.......................\......\.................\reg_8_pack.v

..............................\..............................\...\.......................\.......................\......\.................\risc16f84_clk2x.v

..............................\..............................\...\.......................\.......................\......\.................\rs232_syscon.v

..............................\..............................\...\.......................\.......................\......\.................\serial.v

..............................\..............................\...\.......................\.......................\......\.................\square_wave_dds.v

..............................\..............................\...\.......................\.......................\......\.................\top.v

..............................\..............................\...\.......................\.......................\......\.................\vga_128_by_92.v

..............................\..............................\...\.......................\.......................\......\.................\xilinx_block_ram_3_3.v

..............................\..............................\...\.......................\.......................\......\.................\xilinx_block_ram_8_16.v

..............................\..............................\...\.......................\.......................\......\b13_safe_09_17_02.zip

..............................\..............................\...\.......................\.......................\......\OPENCORES.files\block_diagram.gif

..............................\..............................\...\.......................\.......................\......\...............\dotty.gif

..............................\..............................\...\.......................\.......................\......\...............\title_logo.gif

..............................\..............................\...\.......................\.......................\......\OPENCORES.htm

..............................\..............................\...\.......................\.......................\......\vga_core.htm

..............................\..............................\...\.......................\.......................\......\vga_core.pdf

..............................\..............................\...\.......................\.......................\......\vga_lcd.htm

..............................\..............................\...\...接口设计实例及测试程序\VGA接口设计实例及测试程序\VGA_example\vgainterface\cmp_state.ini

..............................\..............................\...\.........................\.........................\...........\............\code.hex

..............................\..............................\...\.........................\.........................\...........\............\db\altsyncram_fiq.tdf

..............................\..............................\...\.........................\.........................\...........\............\..\altsyncr