文件名称:mskmsk

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2013-04-27
  • 文件大小:
  • 301kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 杨**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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最小移频键控(MSK)是移频键控(FSK)的一种改进型,是一种在无线移动通信中很有吸引力的数字调制方式。-Minimum Shift Keying (MSK) is an improved frequency shift keying (FSK) is a digital modulation scheme in a wireless mobile communication very attractive.
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下载文件列表





mskmsk\automake.log

......\core.tpl

......\coregen_lock

......\dds1_cosine.asy

......\dds1_cosine.edn

......\dds1_cosine.sym

......\dds1_cosine.v

......\dds1_cosine.veo

......\dds1_cosine.vhd

......\dds1_cosine.vho

......\dds1_cosine.xco

......\dds1_cosine_flist.txt

......\dds1_cosine_readme.txt

......\dds1_cosine_SINCOS_TABLE_TRIG_ROM.mif

......\dds1_sine.asy

......\dds1_sine.edn

......\dds1_sine.sym

......\dds1_sine.v

......\dds1_sine.veo

......\dds1_sine.vhd

......\dds1_sine.vho

......\dds1_sine.xco

......\dds1_sine_flist.txt

......\dds1_sine_readme.txt

......\dds1_sine_SINCOS_TABLE_TRIG_ROM.mif

......\dds_modu.asy

......\dds_modu.edn

......\dds_modu.sym

......\dds_modu.v

......\dds_modu.veo

......\dds_modu.vhd

......\dds_modu.vho

......\dds_modu.xco

......\dds_modu_flist.txt

......\dds_modu_readme.txt

......\dds_modu_SINCOS_TABLE_TRIG_ROM.mif

......\iqmodu.v

......\iqsin.v

......\mskmsk.dhp

......\mskmsk.ise

......\mskmsk.ise_ISE_Backup

......\msk_mult.tfi

......\msk_mult.v

......\msk_mult.xaw

......\msk_mult_arwz.ucf

......\msk_top.v

......\msk_top_summary.html

......\s2p.v

......\test.v

......\test_v.fdo

......\test_v.udo

......\transcript

......\vsim.wlf

......\work\dds1_cosine\verilog.asm

......\....\...........\_primary.dat

......\....\...........\_primary.vhd

......\....\.....sine\verilog.asm

......\....\.........\_primary.dat

......\....\.........\_primary.vhd

......\....\..._modu\verilog.asm

......\....\........\_primary.dat

......\....\........\_primary.vhd

......\....\glbl\verilog.asm

......\....\....\_primary.dat

......\....\....\_primary.vhd

......\....\iqmodu\verilog.asm

......\....\......\_primary.dat

......\....\......\_primary.vhd

......\....\..sin\verilog.asm

......\....\.....\_primary.dat

......\....\.....\_primary.vhd

......\....\msk_mult\verilog.asm

......\....\........\_primary.dat

......\....\........\_primary.vhd

......\....\....top\verilog.asm

......\....\.......\_primary.dat

......\....\.......\_primary.vhd

......\....\s2p\verilog.asm

......\....\...\_primary.dat

......\....\...\_primary.vhd

......\....\test_v\verilog.asm

......\....\......\_primary.dat

......\....\......\_primary.vhd

......\....\_info

......\xaw2verilog.log

......\_cg\_cg_exc.in

......\...\_cg_exc.out

......\._projnav\createTF.err

......\.........\mskmsk.gfl

......\.........\msk_mult_jhdparse_tcl.rsp

......\.........\sumrpt_tcl.rsp

......\.........\v2tfi.err

......\__projnav.log

......\work\dds1_cosine

......\....\dds1_sine

......\....\dds_modu

......\....\glbl

......\....\iqmodu

......\....\iqsin

......\....\msk_mult

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