文件名称:div5
介绍说明－－下载内容均来自于网络，请自行研究使用
用verilog描述的任意分频器，包括奇偶分频。-Any divider verilog descr iption, including the parity divide.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
div5\designer\impl1\designer_genhdl.log
....\........\.....\div.tcl
....\div5.prj
....\hdl\div5.v
....\...\waveperl.log
....\simulation\modelsim.ini
....\..........\modelsim.ini.sav
....\..........\modelsim.log
....\..........\postsynth\div\verilog.psm
....\..........\.........\...\_primary.dat
....\..........\.........\...\_primary.dbs
....\..........\.........\...\_primary.vhd
....\..........\.........\_info
....\..........\.resynth\div\verilog.psm
....\..........\........\...\_primary.dat
....\..........\........\...\_primary.dbs
....\..........\........\...\_primary.vhd
....\..........\........\_info
....\..........\run.do
....\..........\vsim.wlf
....\..........\work\div\verilog.psm
....\..........\....\...\_primary.dat
....\..........\....\...\_primary.dbs
....\..........\....\...\_primary.vhd
....\..........\....\_info
....\.martgen\smartgen.aws
....\.ynthesis\div.areasrr
....\.........\div.edn
....\.........\div.fse
....\.........\div.htm
....\.........\div.map
....\.........\div.sap
....\.........\div.sdf
....\.........\div.so
....\.........\div.srd
....\.........\div.srm
....\.........\div.srr
....\.........\div.srs
....\.........\div.tlg
....\.........\div.v
....\.........\div_sdc.sdc
....\.........\div_syn.prj
....\.........\run_options.txt
....\.........\stdout.log
....\.........\.yntmp\div.msg
....\.........\......\div.plg
....\.........\......\div_flink.htm
....\.........\......\div_srr.htm
....\.........\......\div_toc.htm
....\.........\......\sap.log
....\viewdraw\vf\project.lst
....\........\viewdraw.ini
....\designer\impl1\simulation
....\simulation\postsynth\div
....\..........\.........\_temp
....\..........\.resynth\div
....\..........\........\_temp
....\..........\work\div
....\..........\....\_temp
....\designer\impl1
....\simulation\postsynth
....\..........\presynth
....\..........\work
....\.ynthesis\backup
....\.........\syntmp
....\viewdraw\sch
....\........\sym
....\........\vf
....\........\wir
....\component
....\constraint
....\coreconsole
....\designer
....\hdl
....\phy_synthesis
....\simulation
....\smartgen
....\stimulus
....\synthesis
....\viewdraw
div5