文件名称:SPI_fpga_w_r_sigle
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verilog fpga spi slave 收发测试 有简单的协议 modelsim仿真通过 -simple protocol modelsim verilog fpga spi slave transceiver test simulation by
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下载文件列表
SPI_fpga_w_r_sigle
..................\SPI1.archive.rpt
..................\SPI1.done
..................\SPI1.eda.rpt
..................\SPI1.flow.rpt
..................\SPI1.map.rpt
..................\SPI1.map.smsg
..................\SPI1.map.summary
..................\SPI1.qpf
..................\SPI1.qsf
..................\SPI1.qws
..................\SPI1.v
..................\SPI1.v.bak
..................\SPI1_nativelink_simulation.rpt
..................\SPI_W_R.qar
..................\SPI_W_R.qarlog
..................\__SPI1.auto.qarlog
..................\db
..................\..\SPI1.archive.qmsg
..................\..\SPI1.archiver.cache
..................\..\SPI1.cbx.xml
..................\..\SPI1.cmp.rdb
..................\..\SPI1.cmp_merge.kpt
..................\..\SPI1.db_info
..................\..\SPI1.eda.qmsg
..................\..\SPI1.hier_info
..................\..\SPI1.hif
..................\..\SPI1.lpc.html
..................\..\SPI1.lpc.rdb
..................\..\SPI1.lpc.txt
..................\..\SPI1.map.bpm
..................\..\SPI1.map.cdb
..................\..\SPI1.map.hdb
..................\..\SPI1.map.kpt
..................\..\SPI1.map.logdb
..................\..\SPI1.map.qmsg
..................\..\SPI1.map.rdb
..................\..\SPI1.map_bb.cdb
..................\..\SPI1.map_bb.hdb
..................\..\SPI1.map_bb.logdb
..................\..\SPI1.pre_map.cdb
..................\..\SPI1.pre_map.hdb
..................\..\SPI1.qpf
..................\..\SPI1.root_partition.map.reg_db.cdb
..................\..\SPI1.rtlv.hdb
..................\..\SPI1.rtlv_sg.cdb
..................\..\SPI1.rtlv_sg_swap.cdb
..................\..\SPI1.sgdiff.cdb
..................\..\SPI1.sgdiff.hdb
..................\..\SPI1.sld_design_entry.sci
..................\..\SPI1.sld_design_entry_dsc.sci
..................\..\SPI1.smart_action.txt
..................\..\SPI1.syn_hier_info
..................\..\SPI1.tis_db_list.ddb
..................\..\logic_util_heursitic.dat
..................\..\prev_cmp_SPI1.qmsg
..................\incremental_db
..................\..............\README
..................\..............\compiled_partitions
..................\..............\...................\SPI1.db_info
..................\..............\...................\SPI1.root_partition.map.cdb
..................\..............\...................\SPI1.root_partition.map.dpi
..................\..............\...................\SPI1.root_partition.map.hbdb.cdb
..................\..............\...................\SPI1.root_partition.map.hbdb.hb_info
..................\..............\...................\SPI1.root_partition.map.hbdb.hdb
..................\..............\...................\SPI1.root_partition.map.hbdb.sig
..................\..............\...................\SPI1.root_partition.map.hdb
..................\..............\...................\SPI1.root_partition.map.kpt
..................\simulation
..................\..........\modelsim
..................\..........\........\SPI1.vt.bak
..................\..........\........\SPI1_run_msim_rtl_verilog.do
..................\..........\........\SPI1_run_msim_rtl_verilog.do.bak
..................\..........\........\SPI1_run_msim_rtl_verilog.do.bak1
..................\..........\........\SPI1_run_msim_rtl_verilog.do.bak10
..................\..........\........\SPI1_run_msim_rtl_verilog.do.bak11
..................\..........\........\SPI1_run_msim_rtl_verilog.do.bak2
..................\..........\........\SPI1_run_msim_rtl_verilog.do.bak3
..................\..........\........\SPI1_run_msim_rtl_verilog.do.bak4
..................\..........\........\SPI1_run_msim_rtl_verilog.do.bak5
..................\..........\........\SPI1_run_msim_rtl_verilog.do.bak6
..................\..........\........\SPI1_run_msim_rtl_verilog.do.bak7
..................\..........\........\SPI1_run_msim_rtl_verilog.do.bak8
..................\..........\........\SPI1_run_msim_rtl_verilog.do.bak9
..................\..........\........\SPI1_vlg_tst.vt
..................\..........\........\SPI1_vlg_tst.