文件名称:qjq
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基于VHDL的全加器程序，用门电路实现两个二进数相加并求出和的组合线路，就是求二进制数矢量加法的。-Full adder VHDL-based program, with gates to achieve two binary numbers together and find a combination of lines and is seeking the binary vector addition.
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下载文件列表
qjq\qjq.qpf
...\qjq.qsf
...\db\qjq.cmp.rdb
...\..\qjq.db_info
...\..\qjq.eda.qmsg
...\..\prev_cmp_qjq.qmsg
...\..\qjq.sta.rdb
...\..\qjq.sld_design_entry.sci
...\..\qjq.cmp0.ddb
...\..\qjq.asm.rdb
...\..\qjq.map.qmsg
...\..\qjq.lpc.txt
...\..\qjq.fit.qmsg
...\..\qjq.cmp.logdb
...\..\logic_util_heursitic.dat
...\..\qjq.cmp2.ddb
...\..\qjq.lpc.html
...\..\qjq.cbx.xml
...\..\qjq.rtlv.hdb
...\..\qjq.lpc.rdb
...\..\qjq.map_bb.logdb
...\..\qjq.map.cdb
...\..\qjq.smart_action.txt
...\..\qjq.sgdiff.cdb
...\..\qjq.sgdiff.hdb
...\..\qjq.sta.qmsg
...\..\qjq.amm.cdb
...\..\qjq.cmp.cdb
...\..\qjq.rtlv_sg.cdb
...\..\qjq.cmp.hdb
...\..\qjq.sta_cmp.8_slow.tdb
...\..\qjq.idb.cdb
...\..\qjq.rtlv_sg_swap.cdb
...\..\qjq.pre_map.hdb
...\..\qjq.pre_map.cdb
...\..\qjq.sld_design_entry_dsc.sci
...\..\qjq.asm.qmsg
...\..\qjq.asm_labs.ddb
...\..\qjq.hif
...\..\qjq.hier_info
...\..\qjq.map_bb.cdb
...\..\qjq.map.logdb
...\..\qjq.map.hdb
...\..\qjq.map_bb.hdb
...\..\qjq.cmp.bpm
...\..\qjq.cmp1.ddb
...\..\qjq.map.bpm
...\..\qjq.tis_db_list.ddb
...\..\qjq.tmw_info
...\..\qjq.syn_hier_info
...\..\qjq.map.kpt
...\..\qjq.cmp_merge.kpt
...\..\qjq.cmp.kpt
...\qjq.vhd
...\qjq.map.summary
...\qjq.vhd.bak
...\incremental_db\compiled_partitions\qjq.db_info
...\..............\...................\qjq.root_partition.map.kpt
...\..............\...................\qjq.root_partition.map.hbdb.hb_info
...\..............\...................\qjq.root_partition.map.hbdb.sig
...\..............\...................\qjq.root_partition.cmp.logdb
...\..............\...................\qjq.root_partition.cmp.kpt
...\..............\...................\qjq.root_partition.map.cdb
...\..............\...................\qjq.root_partition.map.hdb
...\..............\...................\qjq.root_partition.map.dpi
...\..............\...................\qjq.root_partition.map.hbdb.cdb
...\..............\...................\qjq.root_partition.map.hbdb.hdb
...\..............\...................\qjq.root_partition.cmp.rcfdb
...\..............\...................\qjq.root_partition.cmp.cdb
...\..............\...................\qjq.root_partition.cmp.hdb
...\..............\...................\qjq.root_partition.cmp.dfp
...\..............\README
...\qjq.pin
...\qjq.fit.smsg
...\qjq.fit.summary
...\qjq.sof
...\qjq.pof
...\qjq.done
...\sim\qjq.vht
...\...\qjq.vht.bak
...\...\qjq_modelsim.xrf
...\...\qjq.vho
...\...\qjq_fast.vho
...\...\qjq_vhd.sdo
...\...\qjq_vhd_fast.sdo
...\...\qjq_run_msim_gate_vhdl.do
...\...\gate_work\_info
...\...\.........\_vmake
...\...\.........\qjq\_primary.dbs
...\...\.........\...\_primary.dat
...\...\.........\...\structure.dbs
...\...\.........\...\structure.dat
...\...\.........\...\structure.psm
...\...\.........\...\structure.prw
...\...\qjq.sft
...\...\qjq_run_msim_rtl_vhdl.do
...\...\msim_transcript
...\...\rtl_work\_info
...\...\........\_vmake
...\...\........\qjq\_primary.dbs