文件名称:half_clk
介绍说明－－下载内容均来自于网络，请自行研究使用
此为用Verilog编写的1/2分频器，用以将信号的频率变为原来的2被-This is written using Verilog 1/2 frequency divider for the frequency of the signal into the original two were
(系统自动生成,下载前可以参看下载内容)
下载文件列表
half_clk\Block1.bdf
........\db\half_clk.asm.qmsg
........\..\half_clk.asm_labs.ddb
........\..\half_clk.cbx.xml
........\..\half_clk.cmp.bpm
........\..\half_clk.cmp.cdb
........\..\half_clk.cmp.ecobp
........\..\half_clk.cmp.hdb
........\..\half_clk.cmp.logdb
........\..\half_clk.cmp.rdb
........\..\half_clk.cuda_io_sim_cache.45um_ff_1200mv_n40c_fast.hsd
........\..\half_clk.cuda_io_sim_cache.45um_ii_1200mv_125c_slow.hsd
........\..\half_clk.db_info
........\..\half_clk.eco.cdb
........\..\half_clk.eds_overflow
........\..\half_clk.fit.qmsg
........\..\half_clk.hier_info
........\..\half_clk.hif
........\..\half_clk.map.bpm
........\..\half_clk.map.cdb
........\..\half_clk.map.ecobp
........\..\half_clk.map.hdb
........\..\half_clk.map.logdb
........\..\half_clk.map.qmsg
........\..\half_clk.map_bb.cdb
........\..\half_clk.map_bb.hdb
........\..\half_clk.map_bb.hdbx
........\..\half_clk.map_bb.logdb
........\..\half_clk.pre_map.cdb
........\..\half_clk.pre_map.hdb
........\..\half_clk.psp
........\..\half_clk.root_partition.cmp.atm
........\..\half_clk.root_partition.cmp.dfp
........\..\half_clk.root_partition.cmp.hdbx
........\..\half_clk.root_partition.cmp.logdb
........\..\half_clk.root_partition.cmp.rcf
........\..\half_clk.root_partition.map.atm
........\..\half_clk.root_partition.map.hdbx
........\..\half_clk.root_partition.map.info
........\..\half_clk.rtlv.hdb
........\..\half_clk.rtlv_sg.cdb
........\..\half_clk.rtlv_sg_swap.cdb
........\..\half_clk.sgdiff.cdb
........\..\half_clk.sgdiff.hdb
........\..\half_clk.signalprobe.cdb
........\..\half_clk.sim.cvwf
........\..\half_clk.sim.hdb
........\..\half_clk.sim.qmsg
........\..\half_clk.sim.rdb
........\..\half_clk.sld_design_entry.sci
........\..\half_clk.sld_design_entry_dsc.sci
........\..\half_clk.sta.qmsg
........\..\half_clk.sta.rdb
........\..\half_clk.sta_cmp.7_slow_1200mv_125c.tdb
........\..\half_clk.syn_hier_info
........\..\half_clk.tiscmp.fast_1200mv_n40c.ddb
........\..\half_clk.tiscmp.slow_1200mv_125c.ddb
........\..\half_clk.tiscmp.slow_1200mv_n40c.ddb
........\..\half_clk.tis_db_list.ddb
........\..\half_clk.tmw_info
........\..\prev_cmp_half_clk.asm.qmsg
........\..\prev_cmp_half_clk.fit.qmsg
........\..\prev_cmp_half_clk.map.qmsg
........\..\prev_cmp_half_clk.qmsg
........\..\prev_cmp_half_clk.sim.qmsg
........\..\prev_cmp_half_clk.sta.qmsg
........\..\wed.wsf
........\half_clk.asm.rpt
........\half_clk.bsf
........\half_clk.done
........\half_clk.fit.rpt
........\half_clk.fit.smsg
........\half_clk.fit.summary
........\half_clk.flow.rpt
........\half_clk.map.rpt
........\half_clk.map.summary
........\half_clk.pin
........\half_clk.qpf
........\half_clk.qsf
........\half_clk.qws
........\half_clk.sim.rpt
........\half_clk.sof
........\half_clk.sta.rpt
........\half_clk.sta.summary
........\half_clk.v
........\half_clk.vwf
........\db
half_clk