文件名称:NAND_flash_verilog_vhdl
介绍说明－－下载内容均来自于网络，请自行研究使用
很好的NAND Flash 硬件驱动语言，支持VHDL和verilog 语言方便移植，如果有想用FPGA直接驱动NAND flash而又不知如何下手的朋友肯定喜欢。- NAND Flash Controller Reference Design
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File List
1. RD1055/doc/rd1055.pdf --> NAND Flash Controller Reference Design document
RD1055/doc/rd1055_readme.txt --> Read me file (this file)
2. RD1055/Project/nand_flash_cntl.lpf --> preference file for the design
RD1055/Project/nfcm_tb_vhd.udo_example --> vital glitch removal example
3. /RD1055/simulation/verilog/rtl_verilog.do --> verilog rtl simulation scr ipt
/RD1055/simulation/verilog/timing_verilog.do --> verilog timing simulation scr ipt
/RD1055/simulation/vhdl/rtl_verilog.do --> vhdl rtl simulation scr ipt
/RD1055/simulation/vhdl/timing_verilog.do --> vhdl timing simulation scr ipt
4. RD1055/source/verilog/ACounter.v --> sourc
===============================================================================
File List
1. RD1055/doc/rd1055.pdf --> NAND Flash Controller Reference Design document
RD1055/doc/rd1055_readme.txt --> Read me file (this file)
2. RD1055/Project/nand_flash_cntl.lpf --> preference file for the design
RD1055/Project/nfcm_tb_vhd.udo_example --> vital glitch removal example
3. /RD1055/simulation/verilog/rtl_verilog.do --> verilog rtl simulation scr ipt
/RD1055/simulation/verilog/timing_verilog.do --> verilog timing simulation scr ipt
/RD1055/simulation/vhdl/rtl_verilog.do --> vhdl rtl simulation scr ipt
/RD1055/simulation/vhdl/timing_verilog.do --> vhdl timing simulation scr ipt
4. RD1055/source/verilog/ACounter.v --> sourc
(系统自动生成,下载前可以参看下载内容)
下载文件列表
NAND_flash_verilog_vhdl
.......................\doc
.......................\...\rd1055.pdf
.......................\...\rd1055_readme.txt
.......................\project
.......................\.......\nand_flash_cntl.lpf
.......................\.......\nfcm_tb_vhd.udo_example
.......................\simulation
.......................\..........\verilog
.......................\..........\.......\rtl_verilog.do
.......................\..........\.......\timing_verilog.do
.......................\..........\vhdl
.......................\..........\....\rtl_vhdl.do
.......................\..........\....\timing_vhdl.do
.......................\source
.......................\......\verilog
.......................\......\.......\ACounter.v
.......................\......\.......\ErrLoc.v
.......................\......\.......\H_gen.v
.......................\......\.......\ipexpress
.......................\......\.......\.........\xo
.......................\......\.......\.........\xo2
.......................\......\.......\.........\...\ebr_buffer.lpc
.......................\......\.......\.........\...\ebr_buffer.v
.......................\......\.......\.........\..\ebr_buffer.lpc
.......................\......\.......\.........\..\ebr_buffer.v
.......................\......\.......\.........\xp2
.......................\......\.......\.........\...\ebr_buffer.lpc
.......................\......\.......\.........\...\ebr_buffer.v
.......................\......\.......\MFSM.v
.......................\......\.......\nfcm_top.v
.......................\......\.......\nfcm_top.vhd
.......................\......\.......\TFSM.v
.......................\......\vhdl
.......................\......\....\ACounter.vhd
.......................\......\....\ErrLoc.vhd
.......................\......\....\H_gen.vhd
.......................\......\....\ipexpress
.......................\......\....\.........\xo
.......................\......\....\.........\xo2
.......................\......\....\.........\...\ebr_buffer.lpc
.......................\......\....\.........\...\ebr_buffer.vhd
.......................\......\....\.........\..\ebr_buffer.lpc
.......................\......\....\.........\..\ebr_buffer.vhd
.......................\......\....\.........\xp2
.......................\......\....\.........\...\ebr_buffer.lpc
.......................\......\....\.........\...\ebr_buffer.vhd
.......................\......\....\MFSM.vhd
.......................\......\....\nfcm_top.vhd
.......................\......\....\TFSM.vhd
.......................\testbench
.......................\.........\verilog
.......................\.........\.......\flash_interface.v
.......................\.........\.......\nfcm_tb.v
.......................\.........\vhdl
.......................\.........\....\flash_interface.vhd
.......................\.........\....\nfcm_tb.vhd
RD1055
......\doc
......\...\rd1055.pdf
......\...\rd1055_readme.txt
......\project
......\.......\nand_flash_cntl.lpf
......\.......\nfcm_tb_vhd.udo_example
......\simulation
......\..........\verilog
......\..........\.......\rtl_verilog.do
......\..........\.......\timing_verilog.do
......\..........\vhdl
......\..........\....\rtl_vhdl.do
......\..........\....\timing_vhdl.do
......\source
......\......\verilog
......\......\.......\ACounter.v
......\......\.......\ErrLoc.v
......\......\.......\H_gen.v
......\......\.......\ipexpress
......\......\.......\.........\xo
......\......\.......\.........\xo2
......\......\.......\.........\...\ebr_buffer.lpc
......\......\.......\.........\...\ebr_buffer.v
......\......\.......\.........\..\ebr_buffer.lpc
......\......\.......\.........\..\ebr_buffer.v
......\......\.......\.........\xp2
......\......\.......\.........\...\ebr_buffer.lpc
......\......\.......\.........\...\ebr_buffer.v
......\......\.......\MFSM.v
......\......\.......\nfcm_top.v
......\......\.......\nfcm_top.vhd
......\......\.......\TFSM.v
......\......\vhdl
......\......\....\ACounter.vhd
......\......\....\ErrLoc.vhd
......\......\....\H_gen.vhd
......\......\....\ipexpress
...