文件名称:05_sdram_vga_test
介绍说明－－下载内容均来自于网络，请自行研究使用
VIP FPGA板的配套例子，这个是VGA格式lcd液晶屏幕显示用,通过SDRAM。-VIP FPGA board example.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
05_sdram_vga_test
.................\core
.................\....\sdram_pll.bsf
.................\....\sdram_pll.ppf
.................\....\sdram_pll.qip
.................\....\sdram_pll.v
.................\dev
.................\...\sdram_vga_test.asm.rpt
.................\...\sdram_vga_test.cdf
.................\...\sdram_vga_test.done
.................\...\sdram_vga_test.dpf
.................\...\sdram_vga_test.fit.rpt
.................\...\sdram_vga_test.fit.smsg
.................\...\sdram_vga_test.fit.summary
.................\...\sdram_vga_test.flow.rpt
.................\...\sdram_vga_test.map.rpt
.................\...\sdram_vga_test.map.smsg
.................\...\sdram_vga_test.map.summary
.................\...\sdram_vga_test.pin
.................\...\sdram_vga_test.pof
.................\...\sdram_vga_test.qpf
.................\...\sdram_vga_test.qsf
.................\...\sdram_vga_test.qws
.................\...\sdram_vga_test.sof
.................\...\sdram_vga_test.tan.rpt
.................\...\sdram_vga_test.tan.summary
.................\...\sdram_vga_test.tcl
.................\...\undo_redo.txt
.................\doc
.................\sim
.................\src
.................\...\data_generate.v
.................\...\data_generate.v.bak
.................\...\data_readstream.v
.................\...\lcd_ip.zip
.................\...\sdbank_switch.v.bak
.................\...\sdram_ip.zip
.................\...\sdram_vga_ip
.................\...\............\lcd_ip
.................\...\............\......\doc
.................\...\............\......\...\vga_ctrl.c
.................\...\............\......\...\VGA驱动与实现.pdf
.................\...\............\......\...\特效的代码.v
.................\...\............\......\lcd_display.v
.................\...\............\......\lcd_display.v.bak
.................\...\............\......\lcd_driver.v
.................\...\............\......\lcd_driver.v.bak
.................\...\............\......\lcd_para.v
.................\...\............\......\lcd_para.v.bak
.................\...\............\......\lcd_top.v
.................\...\............\......\lcd_top.v.bak
.................\...\............\sdram_ip
.................\...\............\........\dcfifo_ctrl.v
.................\...\............\........\dcfifo_ctrl.v.bak
.................\...\............\........\rdfifo.bsf
.................\...\............\........\rdfifo.qip
.................\...\............\........\rdfifo.v
.................\...\............\........\rdfifo_wave0.jpg
.................\...\............\........\sdbank_switch.v
.................\...\............\........\sdbank_switch.v.bak
.................\...\............\........\sdram_2fifo_top.v
.................\...\............\........\sdram_2fifo_top.v.bak
.................\...\............\........\sdram_cmd.v
.................\...\............\........\sdram_cmd.v.bak
.................\...\............\........\sdram_ctrl.v
.................\...\............\........\sdram_ctrl.v.bak
.................\...\............\........\sdram_para.v
.................\...\............\........\sdram_top.v
.................\...\............\........\sdram_top.v.bak
.................\...\............\........\sdram_wr_data.v
.................\...\............\........\sdram_wr_data.v.bak
.................\...\............\........\wrfifo.bsf
.................\...\............\........\wrfifo.qip
.................\...\............\........\wrfifo.v
.................\...\............\........\wrfifo_wave0.jpg
.................\...\............\sdram_vga_top.v
.................\...\............\sdram_vga_top.v.bak
.................\...\sdram_vga_test.v
.................\...\sdram_vga_test.v.bak
.................\...\system_ctrl.v
.................\...\system_ctrl.v.bak
.................\...\uart_ip
.................\...\.......\clk_generator.v
.................\...\.......\clk_generator.v.bak
.................\...\.......\uart_receiver.v
.................\...\.......\uart_top.v
.................\...\.......\uart_top.v.bak
.......