文件名称:traditional_fft
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2048点fft的VHDL实现 可综合-2048 FFT implementation synthesis
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下载文件列表
traditional_fft
...............\.ROM2048.v.swp
...............\.ROM3_omega.v.swp
...............\addr_accumulator.v
...............\auto_reset.v
...............\auto_reset_tb.v
...............\b4_unit_david.v
...............\b4_unit_tb.v
...............\center_ctrl.v
...............\center_ctrl_tb.v
...............\clk_div.v
...............\copyfile.exe
...............\fft.cr.mti
...............\fft.mpf
...............\fft2.v
...............\fft2048.v
...............\fft2_b.v
...............\FFT_1024_tb.v
...............\FFT_1024_tb.v.bak
...............\FFT_1024_top.v
...............\input.txt
...............\input_buffer.v
...............\modelsim.ini
...............\mona.out
...............\monb.out
...............\omega_generate_unit.v
...............\pipe_line_b4_top.v
...............\pipe_line_b4_top_tb.v
...............\PQ_RAM.v
...............\PQ_RAM_tb.v
...............\RAM.v
...............\result.out
...............\result.txt
...............\ROM2048.v
...............\ROM20481.v
...............\ROM2_omega.v
...............\ROM3_omega.v
...............\ROM4_omega.v
...............\ROM5_omega.v
...............\ROMDAT.txt
...............\ROMDAT1.txt
...............\rom_addr_generate.v
...............\rotate.v
...............\rotate1.v
...............\s4p1.v
...............\s4p1.v.bak
...............\s4p1_tb.v
...............\transcript
...............\vsim.wlf
...............\wlft1hg43g
...............\wlft6hrd4m
...............\wlft6rxxx2
...............\wlft8tb2rx
...............\wlftc3x8bk
...............\work
...............\....\@f@f@t_1024_tb
...............\....\..............\verilog.asm
...............\....\..............\verilog.psm
...............\....\..............\verilog.rw
...............\....\..............\_primary.dat
...............\....\..............\_primary.dbs
...............\....\..............\_primary.vhd
...............\....\@f@f@t_1024_top
...............\....\...............\verilog.asm
...............\....\...............\verilog.psm
...............\....\...............\verilog.rw
...............\....\...............\_primary.dat
...............\....\...............\_primary.dbs
...............\....\...............\_primary.vhd
...............\....\@p@q_@r@a@m
...............\....\...........\verilog.asm
...............\....\...........\verilog.psm
...............\....\...........\verilog.rw
...............\....\...........\_primary.dat
...............\....\...........\_primary.dbs
...............\....\...........\_primary.vhd
...............\....\@p@q_@r@a@m_tb
...............\....\..............\verilog.psm
...............\....\..............\_primary.dat
...............\....\..............\_primary.dbs
...............\....\..............\_primary.vhd
...............\....\@r@a@m
...............\....\......\verilog.asm
...............\....\......\verilog.psm
...............\....\......\verilog.rw
...............\....\......\_primary.dat
...............\....\......\_primary.dbs
...............\....\......\_primary.vhd
...............\....\@r@o@m2048
...............\....\@r@o@m20481
...............\....\...........\verilog.asm
...............\....\...........\verilog.psm
...............\....\...........\verilog.rw
...............\....\...........\_primary.dat
...............\....\...........\_primary.dbs
...............\....\...........\_primary.vhd
...............\....\..........\verilog.asm
...............\....\..........\verilog.psm
...............\....\..........\verilog.rw
...............\....\..........\_primary.dat