文件名称:Chapter-12
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- [ASM] [源码]
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- 2013-09-30
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12.2 ATA主机控制器设计
12.3 ATA主机控制器Testbench设计 -12.2 ATA host controller design 12.3 ATA host controller Testbench Design
12.3 ATA主机控制器Testbench设计 -12.2 ATA host controller design 12.3 ATA host controller Testbench Design
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下载文件列表
Chapter-12\ata\ata.cr.mti
..........\...\ata.mpf
..........\...\atahost_controller.v
..........\...\atahost_pio_tctrl.v
..........\...\atahost_top.v
..........\...\atahost_wb_slave.v
..........\...\ata_device.v
..........\...\chart\Thumbs.db
..........\...\.....\图12-10.bmp
..........\...\.....\图12-14.bmp
..........\...\.....\图12-15.bmp
..........\...\.....\图12-16.bmp
..........\...\.....\图12-3.bmp
..........\...\.....\图12-4.bmp
..........\...\.....\图12-5.bmp
..........\...\.....\图12-7.bmp
..........\...\.....\图12-8.bmp
..........\...\ro_cnt.v
..........\...\test_bench_top.v
..........\...\timescale.v
..........\...\transcript
..........\...\ud_cnt.v
..........\...\vsim.wlf
..........\...\wave\atahost_controller.bmp
..........\...\....\atahost_pio_tctrl.bmp
..........\...\....\atahost_top.bmp
..........\...\....\atahost_wb_slave.bmp
..........\...\....\ata_device.bmp
..........\...\....\ro_cnt.bmp
..........\...\....\test_bench_top.bmp
..........\...\....\Thumbs.db
..........\...\wb_mast_model.v
..........\...\wb_model_defines.v
..........\...\wb_slv_model.v
..........\...\.ork\atahost_controller\verilog.asm
..........\...\....\..................\_primary.dat
..........\...\....\..................\_primary.vhd
..........\...\....\........pio_tctrl\verilog.asm
..........\...\....\.................\_primary.dat
..........\...\....\.................\_primary.vhd
..........\...\....\........top\verilog.asm
..........\...\....\...........\_primary.dat
..........\...\....\...........\_primary.vhd
..........\...\....\........wb_slave\verilog.asm
..........\...\....\................\_primary.dat
..........\...\....\................\_primary.vhd
..........\...\....\..._device\verilog.asm
..........\...\....\..........\_primary.dat
..........\...\....\..........\_primary.vhd
..........\...\....\ro_cnt\verilog.asm
..........\...\....\......\_primary.dat
..........\...\....\......\_primary.vhd
..........\...\....\......1\verilog.asm
..........\...\....\.......\_primary.dat
..........\...\....\.......\_primary.vhd
..........\...\....\test_bench_top\verilog.asm
..........\...\....\..............\_primary.dat
..........\...\....\..............\_primary.vhd
..........\...\....\ud_cnt\verilog.asm
..........\...\....\......\_primary.dat
..........\...\....\......\_primary.vhd
..........\...\....\wb_mast\verilog.asm
..........\...\....\.......\_primary.dat
..........\...\....\.......\_primary.vhd
..........\...\....\...slv\verilog.asm
..........\...\....\......\_primary.dat
..........\...\....\......\_primary.vhd
..........\...\....\_info
..........\...\....\atahost_controller
..........\...\....\atahost_pio_tctrl
..........\...\....\atahost_top
..........\...\....\atahost_wb_slave
..........\...\....\ata_device
..........\...\....\ro_cnt
..........\...\....\ro_cnt1
..........\...\....\test_bench_top
..........\...\....\ud_cnt
..........\...\....\wb_mast
..........\...\....\wb_slv
..........\...\chart
..........\...\wave
..........\...\work
..........\ata
Chapter-12