文件名称:Chapter-2

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  • 书籍源码
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  • [ASM] [源码]
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  • 2013-09-29
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  • 212kb
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  • shixi******
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介绍说明--下载内容均来自于网络,请自行研究使用

3.1加法树乘法器add_tree_mult设计实例,

3.2查找表乘法器lookup_mult设计实例.

3.3布尔乘法器booth_mult设计实例

3.4移位除法器shift_divider设计实例

-3.1 adder tree multiplier add_tree_mult design example, 3.2 lookup table multiplier lookup_mult design examples. 3.3 Design Example 3.4 Boolean multiplier booth_mult shift divider shift_divider design examples
(系统自动生成,下载前可以参看下载内容)

下载文件列表





2.1\adder

...\adder.cr.mti

...\adder.mpf

...\adder.v

...\adder_testbench.v

...\chart\Thumbs.db

...\.....\图2-2.bmp

...\.....\表2-1.bmp

...\transcript

...\vsim.wlf

...\wave\adder.bmp

...\....\adder_testbench.bmp

...\....\Thumbs.db

...\.ork\adder\verilog.asm

...\....\.....\_primary.dat

...\....\.....\_primary.vhd

...\....\....._testbench\verilog.asm

...\....\...............\_primary.dat

...\....\...............\_primary.vhd

...\....\_info

..2\chart\Thumbs.db

...\.....\图2-4.bmp

...\.....\表2-2.bmp

...\full_add.cr.mti

...\full_add.mpf

...\full_add.v

...\full_add_testbench.v

...\transcript

...\vsim.wlf

...\wave\full_add.bmp

...\....\full_add_testbench.bmp

...\....\Thumbs.db

...\.ork\full_add\verilog.asm

...\....\........\_primary.dat

...\....\........\_primary.vhd

...\....\........_testbench\verilog.asm

...\....\..................\_primary.dat

...\....\..................\_primary.vhd

...\....\_info

..3\adder4.cr.mti

...\adder4.mpf

...\adder4.v

...\adder4_testbench.v

...\chart\Thumbs.db

...\.....\图2-7.bmp

...\transcript

...\vsim.wlf

...\wave\adder4.bmp

...\....\adder4_testbench.bmp

...\....\Thumbs.db

...\.ork\adder4\verilog.asm

...\....\......\_primary.dat

...\....\......\_primary.vhd

...\....\......_testbench\verilog.asm

...\....\................\_primary.dat

...\....\................\_primary.vhd

...\....\_info

..4\chart\Thumbs.db

...\.....\图2-10.bmp

...\coun4_testbench.v

...\count4.cr.mti

...\count4.mpf

...\count4.v

...\transcript

...\vsim.wlf

...\wave\coun4.bmp

...\....\coun4_testbench.bmp

...\....\Thumbs.db

...\.ork\coun4_testbench\verilog.asm

...\....\...............\_primary.dat

...\....\...............\_primary.vhd

...\....\....t4\verilog.asm

...\....\......\_primary.dat

...\....\......\_primary.vhd

...\....\_info

..5\chart\Thumbs.db

...\.....\图2-12.bmp

...\.....\表2-3.bmp

...\count60.cr.mti

...\count60.mpf

...\count60.v

...\count60_testbench.v

...\transcript

...\vsim.wlf

...\wave\count60.bmp

...\....\count60_testbench.bmp

...\....\Thumbs.db

...\.ork\count60\verilog.asm

...\....\.......\_primary.dat

...\....\.......\_primary.vhd

...\....\......._testbench\verilog.asm

...\....\.................\_primary.dat

...\....\.................\_primary.vhd

...\....\_info

..1\work\adder

...\....\adder_testbench

..2\work\full_add

...\....\full_add_testbench

..3\work\adder4

...\....\adder4_testbench

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