文件名称:i2c

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [PDF]
  • 上传时间:
  • 2013-09-14
  • 文件大小:
  • 713kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 谢**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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iic总线编写例,可以借鉴使用,编程Verilog语言。-iic bus prepare cases, you can learn to use Verilog programming language.
(系统自动生成,下载前可以参看下载内容)

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i2c

...\bench

...\.....\CVS

...\.....\...\Entries

...\.....\...\Entries.Extra

...\.....\...\Repository

...\.....\...\Root

...\.....\...\Template

...\.....\verilog

...\.....\.......\CVS

...\.....\.......\...\Entries

...\.....\.......\...\Entries.Extra

...\.....\.......\...\Repository

...\.....\.......\...\Root

...\.....\.......\...\Template

...\.....\.......\i2c_slave_model.v

...\.....\.......\spi_slave_model.v

...\.....\.......\tst_bench_top.v

...\.....\.......\wb_master_model.v

...\CVS

...\...\Entries

...\...\Entries.Extra

...\...\Repository

...\...\Root

...\...\Template

...\doc

...\...\CVS

...\...\...\Entries

...\...\...\Entries.Extra

...\...\...\Repository

...\...\...\Root

...\...\...\Template

...\...\i2c_specs.pdf

...\...\src

...\...\...\CVS

...\...\...\...\Entries

...\...\...\...\Entries.Extra

...\...\...\...\Repository

...\...\...\...\Root

...\...\...\...\Template

...\...\...\I2C_specs.doc

...\rtl

...\...\CVS

...\...\...\Entries

...\...\...\Entries.Extra

...\...\...\Repository

...\...\...\Root

...\...\...\Template

...\...\verilog

...\...\.......\CVS

...\...\.......\...\Entries

...\...\.......\...\Entries.Extra

...\...\.......\...\Repository

...\...\.......\...\Root

...\...\.......\...\Template

...\...\.......\i2c_master_bit_ctrl.v

...\...\.......\i2c_master_byte_ctrl.v

...\...\.......\i2c_master_defines.v

...\...\.......\i2c_master_top.v

...\...\.......\timescale.v

...\...\vhdl

...\...\....\CVS

...\...\....\...\Entries

...\...\....\...\Entries.Extra

...\...\....\...\Repository

...\...\....\...\Root

...\...\....\...\Template

...\...\....\I2C.VHD

...\...\....\i2c_master_bit_ctrl.vhd

...\...\....\i2c_master_byte_ctrl.vhd

...\...\....\i2c_master_top.vhd

...\...\....\readme

...\...\....\tst_ds1621.vhd

...\sim

...\...\CVS

...\...\...\Entries

...\...\...\Entries.Extra

...\...\...\Repository

...\...\...\Root

...\...\...\Template

...\...\i2c_verilog

...\...\...........\CVS

...\...\...........\...\Entries

...\...\...........\...\Entries.Extra

...\...\...........\...\Repository

...\...\...........\...\Root

...\...\...........\...\Template

...\...\...........\run

...\...\...........\...\bench.vcd

...\...\...........\...\CVS

...\...\...........\...\...\Entries

...\...\...........\...\...\Entries.Extra

...\...\...........\...\...\Repository

...\...\...........\...\...\Root

...\...\...........\...\...\Template

...\...\...........\...\ncverilog.key

...\...\...........\...\ncverilog.log

...\...\...........\...\run

...\software

...\........\CVS

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