文件名称:dvi-code-verilog
- 所属分类：
- 图形图像处理(光照,映射..)
- 资源属性：
- [C/C++] [源码]
- 上传时间：
- 2013-09-10
- 文件大小：
- 155kb
- 下载次数：
- 0次
- 提 供 者：
- l**
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
dvi encoder and decoder for fpga
(系统自动生成,下载前可以参看下载内容)
下载文件列表
dvi code verilog\model\CY7C1338G_FT.v
................\.....\CY7C1338G_FT_.v
................\.....\dvi_patten_gen.v
................\.....\mcu_stimulus.vhd
................\.....\patten_gen.v
................\.....\patten_gen_with_btn.v
................\.....\patten_sel.v
................\.....\swap_ctrl.v
................\.....\vga2.vhd
................\.....\VGA_Controller.v
................\.....\VGA_Param.h
................\.....\vssver.scc
................\rtl\clk_ctrl.v
................\...\.ommon\debnce.v
................\...\......\hdclrbar.v
................\...\......\synchro.v
................\...\......\timing.v
................\...\......\vssver.scc
................\...\..re_gen\coregen.cgp
................\...\........\vssver.scc
................\...\ctrl_main.ucf
................\...\ctrl_main.v
................\...\dvi_ctrl.v
................\...\....ip\chnlbond.v
................\...\......\.ore\dvi_tx_fifo.coe
................\...\......\....\dvi_tx_fifo.mif
................\...\......\....\dvi_tx_fifo.ngc
................\...\......\....\dvi_tx_fifo.v
................\...\......\....\dvi_tx_fifo.veo
................\...\......\....\dvi_tx_fifo.xco
................\...\......\....\dvi_tx_fifo_blk_mem_gen_v2_8_xst_1.ngc_xst.xrpt
................\...\......\....\dvi_tx_fifo_flist.txt
................\...\......\....\dvi_tx_fifo_readme.txt
................\...\......\....\dvi_tx_fifo_xmdf.tcl
................\...\......\....\inputbuffer.ngc
................\...\......\....\inputbuffer.vhd
................\...\......\....\inputbuffer.vho
................\...\......\....\inputbuffer.xco
................\...\......\....\inputbuffer_blk_mem_gen_v2_8_xst_1.ngc_xst.xrpt
................\...\......\....\inputbuffer_flist.txt
................\...\......\....\inputbuffer_readme.txt
................\...\......\....\inputbuffer_xmdf.tcl
................\...\......\dcminit.v
................\...\......\decode.v
................\...\......\DRAM16XN.v
................\...\......\dvi_decoder.v
................\...\......\dvi_encoder.v
................\...\......\dvi_ip.v
................\...\......\encode.v
................\...\......\patten_gen.v
................\...\......\phsaligner.v
................\...\......\resync_1024fifo.v
................\...\......\resync_part_new.vhd
................\...\......\serdes_4b_10to1_fifo.v
................\...\......\sync_monitor.v
................\...\......\tmds_1c_1to10.v
................\...\......\vssver.scc
................\...\......\watch_dog.v
................\...\new_resync\inputbuffer.ngc
................\...\..........\inputbuffer.vhd
................\...\..........\inputbuffer.vho
................\...\..........\inputbuffer.xco
................\...\..........\inputbuffer_blk_mem_gen_v2_8_xst_1.ngc_xst.xrpt
................\...\..........\inputbuffer_flist.txt
................\...\..........\inputbuffer_readme.txt
................\...\..........\inputbuffer_xmdf.tcl
................\...\..........\resync_part_new.vhd
................\...\reset_gen.v
................\...\trig_cnt.v
................\...\up_registers.v
................\...\vsync_stu_led.v
................\sim\clean_project.bat
................\...\dvi_demo.mpf
................\...\dvi_tx_fifo.mif
................\...\gamma_data.TXT
................\...\glbl.v
................\...\glbl_set.h
................\...\reg_data.TXT
................\...\reg_dataa.TXT
................\...\restart
................\...\s3a_logo.v
................\...\sim.td
................\...\sram_data.TXT
................\...\tb_dvi_demo.v
................\...\vlog.opt
................\...\vssver.scc
................\.yn\div_test.prj
................\...\glbl_set.h
................\version.txt
................\rtl\core_gen\tmp\_cg
................\...\........\tmp
................\...\dvi_ip\core
................\...\common
................\...\core_gen
................\...\dvi_ip
................\...\new_resync
................\model
................\rtl
................\sim
................\syn