文件名称:xapp386
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This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in
a Xilinx® CoolRunner™ -II CPLD. CoolRunner-II CPLDs are the lowest power CPLDs available,
making this the perfect target device for an SPI Master.-This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in
a Xilinx® CoolRunner™ -II CPLD. CoolRunner-II CPLDs are the lowest power CPLDs available,
making this the perfect target device for an SPI Master.
a Xilinx® CoolRunner™ -II CPLD. CoolRunner-II CPLDs are the lowest power CPLDs available,
making this the perfect target device for an SPI Master.-This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in
a Xilinx® CoolRunner™ -II CPLD. CoolRunner-II CPLDs are the lowest power CPLDs available,
making this the perfect target device for an SPI Master.
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xapp386.pdf