文件名称:WXZ
介绍说明－－下载内容均来自于网络，请自行研究使用
加法器是产生数的和的装置。加数和被加数为输入，和数与进位为输出的装置为半加器。若加数、被加数与低位的进位数为输入，而和数与进位为输出则为全加器。常用作计算机算术逻辑部件，执行逻辑操作、移位与指令调用。在电子学中，加法器是一种数位电路，其可进行数字的加法计算。在现代的电脑中，加法器存在于算术逻辑单元（ALU）之中。 加法器可以用来表示各种数值，如：BCD、加三码，主要的加法器是以二进制作运算。由于负数可用二的补数来表示，所以加减器也就不那么必要。-The adder is generated the number of and apparatus. Addend and augend input sum and carry bits of the output means is a half adder. If the addend, augend and the low decimal input, and the sum and carry output is a full adder. Commonly used for computer arithmetic logic unit, perform logical operations, shift instruction calls. In electronics, the adder is a digital circuit, which may be a digital sum. In modern computers, the adder is present being in the arithmetic logic unit (ALU). Adder can be used to represent various values , such as: BCD, plus three yards main adder based on binary for computing. Negative two s complement available to represent the addition and subtraction is not so necessary
(系统自动生成,下载前可以参看下载内容)
下载文件列表
WXZ
...\WXZ.asm.rpt
...\WXZ.done
...\WXZ.fit.eqn
...\WXZ.fit.rpt
...\WXZ.fit.summary
...\WXZ.flow.rpt
...\WXZ.map.eqn
...\WXZ.map.rpt
...\WXZ.map.summary
...\WXZ.pin
...\WXZ.pof
...\WXZ.qpf
...\WXZ.qsf
...\WXZ.sim.rpt
...\WXZ.sof
...\WXZ.tan.rpt
...\WXZ.tan.summary
...\WXZ.v
...\WXZ.vwf
...\db
...\..\WXZ.asm.qmsg
...\..\WXZ.cbx.xml
...\..\WXZ.cmp.cdb
...\..\WXZ.cmp.hdb
...\..\WXZ.cmp.rdb
...\..\WXZ.cmp.tdb
...\..\WXZ.cmp0.ddb
...\..\WXZ.db_info
...\..\WXZ.eco.cdb
...\..\WXZ.eds_overflow
...\..\WXZ.fit.qmsg
...\..\WXZ.hier_info
...\..\WXZ.hif
...\..\WXZ.map.cdb
...\..\WXZ.map.hdb
...\..\WXZ.map.qmsg
...\..\WXZ.pre_map.cdb
...\..\WXZ.pre_map.hdb
...\..\WXZ.psp
...\..\WXZ.rtlv.hdb
...\..\WXZ.rtlv_sg.cdb
...\..\WXZ.rtlv_sg_swap.cdb
...\..\WXZ.sgdiff.cdb
...\..\WXZ.sgdiff.hdb
...\..\WXZ.signalprobe.cdb
...\..\WXZ.sim.hdb
...\..\WXZ.sim.qmsg
...\..\WXZ.sim.rdb
...\..\WXZ.sim.vwf
...\..\WXZ.sld_design_entry.sci
...\..\WXZ.sld_design_entry_dsc.sci
...\..\WXZ.syn_hier_info
...\..\WXZ.tan.qmsg
...\..\WXZ_cmp.qrpt
...\..\WXZ_sim.qrpt