文件名称:caitiao
介绍说明－－下载内容均来自于网络，请自行研究使用
QuartusII软件写的四条竖彩条信号，通过ADV7171芯片转成模拟信号在监视屏上显示。-The color bar signal which are writen by VHDL ，with the data of the signal converted to analog signal by ADV7171 ，are showed on TV monitor .
(系统自动生成,下载前可以参看下载内容)
下载文件列表
caitiao
.......\.sopc_builder
.......\.............\filters.xml
.......\Design.asm.rpt
.......\Design.cdf
.......\Design.done
.......\Design.dpf
.......\Design.eda.rpt
.......\Design.fit.rpt
.......\Design.fit.smsg
.......\Design.fit.summary
.......\Design.flow.rpt
.......\Design.map.rpt
.......\Design.map.summary
.......\Design.pin
.......\Design.qpf
.......\Design.qsf
.......\Design.qws
.......\Design.sim.rpt
.......\Design.sof
.......\Design.sta.rpt
.......\Design.sta.summary
.......\Design.vhd
.......\Design.vhd.bak
.......\Design.vwf
.......\I2C_ADV7171.vhd
.......\I2C_ADV7171.vhd.bak
.......\I2C_TVP5150.vhd
.......\I2C_TVP5150.vhd.bak
.......\Re_毕设答疑.zip
.......\SAV_check.vhd
.......\SAV_check.vhd.bak
.......\caitiao.vhd
.......\caitiao.vhd.bak
.......\converter.vhd
.......\converter.vhd.bak
.......\db
.......\..\Design.asm.qmsg
.......\..\Design.asm_labs.ddb
.......\..\Design.cbx.xml
.......\..\Design.cmp.bpm
.......\..\Design.cmp.cdb
.......\..\Design.cmp.ecobp
.......\..\Design.cmp.hdb
.......\..\Design.cmp.kpt
.......\..\Design.cmp.logdb
.......\..\Design.cmp.rdb
.......\..\Design.cmp_merge.kpt
.......\..\Design.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
.......\..\Design.cuda_io_sim_cache.45um_tt_1200mv_85c_slow.hsd
.......\..\Design.db_info
.......\..\Design.eco.cdb
.......\..\Design.eda.qmsg
.......\..\Design.eds_overflow
.......\..\Design.fit.qmsg
.......\..\Design.hier_info
.......\..\Design.hif
.......\..\Design.lpc.html
.......\..\Design.lpc.rdb
.......\..\Design.lpc.txt
.......\..\Design.map.bpm
.......\..\Design.map.cdb
.......\..\Design.map.ecobp
.......\..\Design.map.hdb
.......\..\Design.map.kpt
.......\..\Design.map.logdb
.......\..\Design.map.qmsg
.......\..\Design.map_bb.cdb
.......\..\Design.map_bb.hdb
.......\..\Design.map_bb.logdb
.......\..\Design.pre_map.cdb
.......\..\Design.pre_map.hdb
.......\..\Design.rtlv.hdb
.......\..\Design.rtlv_sg.cdb
.......\..\Design.rtlv_sg_swap.cdb
.......\..\Design.sgdiff.cdb
.......\..\Design.sgdiff.hdb
.......\..\Design.sim.cvwf
.......\..\Design.sim.hdb
.......\..\Design.sim.qmsg
.......\..\Design.sim.rdb
.......\..\Design.sld_design_entry.sci
.......\..\Design.sld_design_entry_dsc.sci
.......\..\Design.smp_dump.txt
.......\..\Design.sta.qmsg
.......\..\Design.sta.rdb
.......\..\Design.sta_cmp.6_slow_1200mv_85c.tdb
.......\..\Design.syn_hier_info
.......\..\Design.tis_db_list.ddb
.......\..\Design.tiscmp.fast_1200mv_0c.ddb
.......\..\Design.tiscmp.slow_1200mv_0c.ddb
.......\..\Design.tiscmp.slow_1200mv_85c.ddb
.......\..\Design.tmw_info
.......\..\Design_global_asgn_op.abo
.......\..\prev_cmp_Design.asm.qmsg
.......\..\prev_cmp_Design.eda.qmsg
.......\..\prev_cmp_Design.fit.qmsg
.......\..\prev_cmp_Design.map.qmsg
.......\..\prev_cmp_Design.qmsg
.......\..\prev_cmp_Design.sim.qmsg