文件名称:coa
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在Modelsim中实现类MIPS多周期流水化处理器-In Modelsim achieve class multi-cycle pipelined processor MIPS
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下载文件列表
COD_project\Add.v
...........\ALU_control.v
...........\ALU_control.v.bak
...........\And.v
...........\Control.v
...........\Control.v.bak
...........\CPU_design.cr.mti
...........\CPU_design.mpf
...........\CPU_pro.cr.mti
...........\CPU_pro.mpf
...........\data.txt
...........\EX_ALU.v
...........\EX_ALU.v.bak
...........\EX_MEM_reg.v
...........\EX_MEM_reg.v.bak
...........\EX_Mux1.v
...........\EX_Mux1.v.bak
...........\EX_Mux2.v
...........\EX_Mux2.v.bak
...........\EX_Mux3.v
...........\EX_Mux3.v.bak
...........\EX_Mux4.v
...........\EX_Mux4.v.bak
...........\Forwarding_unit.v
...........\Forwarding_unit.v.bak
...........\ID_EX_reg.v
...........\ID_EX_reg.v.bak
...........\ID_Hazard.v
...........\ID_Hazard.v.bak
...........\IF_ID_reg.v
...........\IF_ID_reg.v.bak
...........\IF_IM.v
...........\IF_IM.v.bak
...........\MEM_Branch.v
...........\MEM_Branch.v.bak
...........\MEM_DM.v
...........\MEM_DM.v.bak
...........\MEM_WB_reg.v
...........\MEM_WB_reg.v.bak
...........\MUX_ID.v
...........\MUX_ID.v.bak
...........\MUX_IF.v
...........\MUX_IF.v.bak
...........\MUX_WB.v
...........\PC.v
...........\PC.v.bak
...........\PC_plus_4.v
...........\PC_plus_4.v.bak
...........\Registers.v
...........\Registers.v.bak
...........\reg_b.v
...........\reg_b.v.bak
...........\result.txt
...........\Shift_left_2.v
...........\Sign_extend.v
...........\Sign_extend.v.bak
...........\top.v
...........\top.v.bak
...........\top2.v
...........\top2.v.bak
...........\transcript
...........\vsim.wlf
...........\work\@a@l@u_control\verilog.asm
...........\....\..............\_primary.dat
...........\....\..............\_primary.dbs
...........\....\..............\_primary.vhd
...........\....\..dd\verilog.asm
...........\....\....\_primary.dat
...........\....\....\_primary.dbs
...........\....\....\_primary.vhd
...........\....\..nd\verilog.asm
...........\....\....\_primary.dat
...........\....\....\_primary.dbs
...........\....\....\_primary.vhd
...........\....\.control\transcript
...........\....\........\verilog.asm
...........\....\........\_primary.dat
...........\....\........\_primary.dbs
...........\....\........\_primary.vhd
...........\....\.e@x_@a@l@u\verilog.asm
...........\....\...........\_primary.dat
...........\....\...........\_primary.dbs
...........\....\...........\_primary.vhd
...........\....\......m@e@m_reg\verilog.asm
...........\....\...............\_primary.dat
...........\....\...............\_primary.dbs
...........\....\...............\_primary.vhd
...........\....\.......ux1\verilog.asm
...........\....\..........\_primary.dat
...........\....\..........\_primary.dbs
...........\....\..........\_primary.vhd
...........\....\.........2\verilog.asm
...........\....\..........\_primary.dat
...........\....\..........\_primary.dbs
...........\....\..........\_primary.vhd
...........\....\.........3\verilog.asm
...........\....\..........\_primary.dat
...........\....\..........\_primary.dbs
...........\....\..........\_primary.vhd
...........\....\.........4\verilog.asm