文件名称:TCON
介绍说明－－下载内容均来自于网络，请自行研究使用
用verilog编程的TCON模块（时序控制器）的程序-Verilog programming module with TCON (timing controller) program
(系统自动生成,下载前可以参看下载内容)
下载文件列表
TCON\gene_clk\db\gene_clk.cbx.xml
....\........\..\gene_clk.cmp.rdb
....\........\..\gene_clk.dbp
....\........\..\gene_clk.db_info
....\........\..\gene_clk.eco.cdb
....\........\..\gene_clk.hier_info
....\........\..\gene_clk.hif
....\........\..\gene_clk.map.bpm
....\........\..\gene_clk.map.cdb
....\........\..\gene_clk.map.ecobp
....\........\..\gene_clk.map.hdb
....\........\..\gene_clk.map.logdb
....\........\..\gene_clk.map.qmsg
....\........\..\gene_clk.map_bb.cdb
....\........\..\gene_clk.map_bb.hdb
....\........\..\gene_clk.map_bb.logdb
....\........\..\gene_clk.pre_map.cdb
....\........\..\gene_clk.pre_map.hdb
....\........\..\gene_clk.psp
....\........\..\gene_clk.pss
....\........\..\gene_clk.rtlv.hdb
....\........\..\gene_clk.rtlv_sg.cdb
....\........\..\gene_clk.rtlv_sg_swap.cdb
....\........\..\gene_clk.sgdiff.cdb
....\........\..\gene_clk.sgdiff.hdb
....\........\..\gene_clk.sld_design_entry.sci
....\........\..\gene_clk.sld_design_entry_dsc.sci
....\........\..\gene_clk.syn_hier_info
....\........\..\gene_clk.tis_db_list.ddb
....\........\gene_clk.done
....\........\gene_clk.flow.rpt
....\........\gene_clk.map.rpt
....\........\gene_clk.map.summary
....\........\gene_clk.qpf
....\........\gene_clk.qsf
....\........\gene_clk.qws
....\........\RTL\gene_clk.v
....\........\...\gene_clk.v.bak
....\........\...\TCON_define.v
....\........_tb\gene_clk.v
....\...........\gene_clk_tb.cr.mti
....\...........\gene_clk_tb.mpf
....\...........\gene_clk_tb.v
....\...........\gene_clk_tb.v.bak
....\...........\TCON_define.v
....\...........\transcript
....\...........\vsim.wlf
....\...........\work\@_opt\vopt2gwxg4
....\...........\....\.....\vopt6bdtqg
....\...........\....\.....\vopt9v2qqg
....\...........\....\.....\voptdbrkqg
....\...........\....\.....\voptgbig7f
....\...........\....\.....\voptgfce16
....\...........\....\.....\voptkv7d7f
....\...........\....\.....\voptkz1a16
....\...........\....\.....\voptqfq716
....\...........\....\.....\voptvfh4h4
....\...........\....\.....\voptyz61h4
....\...........\....\.....\_deps
....\...........\....\gene_clk\verilog.asm
....\...........\....\........\verilog.rw
....\...........\....\........\_primary.dat
....\...........\....\........\_primary.dbs
....\...........\....\........\_primary.vhd
....\...........\....\........_tb\verilog.asm
....\...........\....\...........\verilog.rw
....\...........\....\...........\_primary.dat
....\...........\....\...........\_primary.dbs
....\...........\....\...........\_primary.vhd
....\...........\....\_info
....\...........\....\_vmake
....\TCON\db\TCON.cbx.xml
....\....\..\TCON.cmp.rdb
....\....\..\TCON.dbp
....\....\..\TCON.db_info
....\....\..\TCON.eco.cdb
....\....\..\TCON.hier_info
....\....\..\TCON.hif
....\....\..\TCON.map.bpm
....\....\..\TCON.map.cdb
....\....\..\TCON.map.ecobp
....\....\..\TCON.map.hdb
....\....\..\TCON.map.logdb
....\....\..\TCON.map.qmsg
....\....\..\TCON.map_bb.cdb
....\....\..\TCON.map_bb.hdb
....\....\..\TCON.map_bb.logdb
....\....\..\TCON.pre_map.cdb
....\....\..\TCON.pre_map.hdb
....\....\..\TCON.psp
....\....\..\TCON.pss
....\....\..\TCON.rtlv.hdb
....\....\..\TCON.rtlv_sg.cdb
....\....\..\TCON.rtlv_sg_swap.cdb
....\....\..\TCON.sgdiff.cdb
....\....\..\TCON.sgdiff.hdb
....\....\..\TCON.sld_design_entry.sci
....\....\..\TCON.sld_design_entry_dsc.sci
....\....\..\TCON.smp_dump.txt
....\....\..\TCON.syn_hier_info