LAB 2\colormap.v

.....\db\altsyncram_0eq1.tdf

.....\..\altsyncram_7ri2.tdf

.....\..\altsyncram_i1l1.tdf

.....\..\altsyncram_k4p3.tdf

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.....\..\design.cmp_merge.kpt

.....\..\design.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd

.....\..\design.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd

.....\..\design.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd

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.....\..\design.hif

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.....\..\design.map_bb.cdb

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.....\..\design.map_bb.logdb

.....\..\design.pre_map.cdb

.....\..\design.pre_map.hdb

.....\..\design.root_partition.map.reg_db.cdb

.....\..\design.rtlv.hdb

.....\..\design.rtlv_sg.cdb

.....\..\design.rtlv_sg_swap.cdb

.....\..\design.sgdiff.cdb

.....\..\design.sgdiff.hdb

.....\..\design.sld_design_entry.sci

.....\..\design.sld_design_entry_dsc.sci

.....\..\design.smart_action.txt

.....\..\design.sta.qmsg

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.....\..\design.sta_cmp.7_slow_1200mv_85c.tdb

.....\..\design.syn_hier_info

.....\..\design.tiscmp.fast_1200mv_0c.ddb

.....\..\design.tiscmp.slow_1200mv_0c.ddb

.....\..\design.tiscmp.slow_1200mv_85c.ddb

.....\..\design.tis_db_list.ddb

.....\..\design.tmw_info

.....\..\logic_util_heursitic.dat

.....\..\mux_foc.tdf

.....\..\mux_jib.tdf

.....\..\prev_cmp_design.map.qmsg

.....\..\prev_cmp_design.qmsg

.....\..\wed.zsf

.....\design.asm.rpt

.....\design.bdf

.....\design.cdf

.....\design.done

.....\design.fit.rpt

.....\design.fit.smsg

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.....\design.sta.rpt

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.....\design.tan.rpt

.....\design.tan.summary

.....\design.vwf

.....\design_assignment_defaults.qdf