文件名称:UART_VHDLCodes
介绍说明－－下载内容均来自于网络，请自行研究使用
基于VHDL的异步串口收发器，在FPGA上设计Uart接收模块实现从pc接收串口数据；
在FPGA上设计Uart发送模块，把从pc接收的数据的16进制值加1再发送给PC；
设计单片机和FPGA接口模块，把接收到的数据送给单片机，并显示在LCD上
-VHDL-based asynchronous serial transceivers Uart receive module in the FPGA design from pc to receive serial data design the Uart send module on FPGA, the hexadecimal value of the data received from the pc plus 1 and then sent to a PC design microcontroller and FPGA interface module, the received data sent to the MCU, and displayed on the LCD
在FPGA上设计Uart发送模块，把从pc接收的数据的16进制值加1再发送给PC；
设计单片机和FPGA接口模块，把接收到的数据送给单片机，并显示在LCD上
-VHDL-based asynchronous serial transceivers Uart receive module in the FPGA design from pc to receive serial data design the Uart send module on FPGA, the hexadecimal value of the data received from the pc plus 1 and then sent to a PC design microcontroller and FPGA interface module, the received data sent to the MCU, and displayed on the LCD
(系统自动生成,下载前可以参看下载内容)
下载文件列表
UART_VHDLCodes\lcd.c
..............\UART\ALL.bdf
..............\....\baud_generator.bsf
..............\....\baud_generator.vhd
..............\....\db\UART122001.asm.qmsg
..............\....\..\UART122001.cbx.xml
..............\....\..\UART122001.cmp.cdb
..............\....\..\UART122001.cmp.hdb
..............\....\..\UART122001.cmp.qrpt
..............\....\..\UART122001.cmp.rdb
..............\....\..\UART122001.cmp.tdb
..............\....\..\UART122001.cmp0.ddb
..............\....\..\UART122001.cmp2.ddb
..............\....\..\UART122001.dbp
..............\....\..\UART122001.db_info
..............\....\..\UART122001.eco.cdb
..............\....\..\UART122001.fit.qmsg
..............\....\..\UART122001.hier_info
..............\....\..\UART122001.hif
..............\....\..\UART122001.map.cdb
..............\....\..\UART122001.map.hdb
..............\....\..\UART122001.map.qmsg
..............\....\..\UART122001.pre_map.cdb
..............\....\..\UART122001.pre_map.hdb
..............\....\..\UART122001.psp
..............\....\..\UART122001.rtlv.hdb
..............\....\..\UART122001.rtlv_sg.cdb
..............\....\..\UART122001.rtlv_sg_swap.cdb
..............\....\..\UART122001.sgdiff.cdb
..............\....\..\UART122001.sgdiff.hdb
..............\....\..\UART122001.signalprobe.cdb
..............\....\..\UART122001.sld_design_entry.sci
..............\....\..\UART122001.sld_design_entry_dsc.sci
..............\....\..\UART122001.syn_hier_info
..............\....\..\UART122001.tan.qmsg
..............\....\UART122001.asm.rpt
..............\....\UART122001.cdf
..............\....\UART122001.done
..............\....\UART122001.fit.eqn
..............\....\UART122001.fit.rpt
..............\....\UART122001.fit.summary
..............\....\UART122001.flow.rpt
..............\....\UART122001.map.eqn
..............\....\UART122001.map.rpt
..............\....\UART122001.map.summary
..............\....\UART122001.pin
..............\....\UART122001.pof
..............\....\UART122001.qpf
..............\....\UART122001.qsf
..............\....\UART122001.qws
..............\....\UART122001.sof
..............\....\UART122001.tan.rpt
..............\....\UART122001.tan.summary
..............\....\UART_receiver.bsf
..............\....\UART_receiver.vhd
..............\....\UART_transmitter.bsf
..............\....\UART_transmitter.vhd
..............\....\db
..............\UART
UART_VHDLCodes