压缩包 : 83390049xapp485.zip 列表
xapp_485/
xapp_485/4bit_constraints/
xapp_485/4bit_constraints/Copy of top4_rx_3s500e_fg320_tl_a.ucf
xapp_485/4bit_constraints/top4_rx_3s100e_cp132_t_a.ucf
xapp_485/4bit_constraints/top4_rx_3s100e_vq100_t_a.ucf
xapp_485/4bit_constraints/top4_rx_3s1200e_fg320_tl_a.ucf
xapp_485/4bit_constraints/top4_rx_3s1200e_fg320_tr_a.ucf
xapp_485/4bit_constraints/top4_rx_3s1200e_ft256_tl_a.ucf
xapp_485/4bit_constraints/top4_rx_3s1200e_ft256_tr_a.ucf
xapp_485/4bit_constraints/top4_rx_3s1600e_fg320_tl_a.ucf
xapp_485/4bit_constraints/top4_rx_3s1600e_fg320_tr_a.ucf
xapp_485/4bit_constraints/top4_rx_3s1600e_fg484_tl_a.ucf
xapp_485/4bit_constraints/top4_rx_3s250e_cp132_t_a.ucf
xapp_485/4bit_constraints/top4_rx_3s250e_ft256_tl_a.ucf
xapp_485/4bit_constraints/top4_rx_3s250e_ft256_tr_a.ucf
xapp_485/4bit_constraints/top4_rx_3s250e_pq208_tl_a.ucf
xapp_485/4bit_constraints/top4_rx_3s250e_pq208_tr_a.ucf
xapp_485/4bit_constraints/top4_rx_3s250e_vq100_t_a.ucf
xapp_485/4bit_constraints/top4_rx_3s500e_cp132_t_a.ucf
xapp_485/4bit_constraints/top4_rx_3s500e_fg320_tl_a.ucf
xapp_485/4bit_constraints/top4_rx_3s500e_ft256_tl_a.ucf
xapp_485/4bit_constraints/top4_rx_3s500e_ft256_tr_a.ucf
xapp_485/4bit_constraints/top4_rx_3s500e_pq208_tl_a.ucf
xapp_485/4bit_constraints/top4_rx_3s500e_pq208_tr_a.ucf
xapp_485/4bit_floorplans/
xapp_485/4bit_floorplans/top4_rx_3s100e_vq100_t_a.ppt
xapp_485/4bit_floorplans/top4_rx_3s1200e_fg320_tl_a.ppt
xapp_485/4bit_floorplans/top4_rx_3s1200e_fg320_tr_a.ppt
xapp_485/4bit_floorplans/top4_rx_3s1200e_ft256_tl_a.ppt
xapp_485/4bit_floorplans/top4_rx_3s1200e_ft256_tr_a.ppt
xapp_485/4bit_floorplans/top4_rx_3s1600e_fg320_tl_a.ppt
xapp_485/4bit_floorplans/top4_rx_3s1600e_fg320_tr_a.ppt
xapp_485/4bit_floorplans/top4_rx_3s1600e_fg484_tl_a.ppt
xapp_485/4bit_floorplans/top4_rx_3s250e_cp132_t_a.ppt
xapp_485/4bit_floorplans/top4_rx_3s250e_ft256_tl_a.ppt
xapp_485/4bit_floorplans/top4_rx_3s250e_ft256_tr_a.ppt
xapp_485/4bit_floorplans/top4_rx_3s250e_vq100_t_a.ppt
xapp_485/4bit_floorplans/top4_rx_3s500e_cp132_t_a.ppt
xapp_485/4bit_floorplans/top4_rx_3s500e_fg320_tl_a.ppt
xapp_485/4bit_floorplans/top4_rx_3s500e_ft256_tl_a.ppt
xapp_485/4bit_floorplans/top4_rx_3s500e_ft256_tr_a.ppt
xapp_485/4bit_floorplans/top4_tx_3s100e_cp132_r_a.ppt
xapp_485/4bit_floorplans/top4_tx_3s100e_vq100_r_a.ppt
xapp_485/4bit_floorplans/top4_tx_3s1200e_ft256_rb_a.ppt
xapp_485/4bit_floorplans/top4_tx_3s1200e_ft256_rt_a.ppt
xapp_485/4bit_floorplans/top4_tx_3s250e_cp132_a.ppt
xapp_485/4bit_floorplans/top4_tx_3s250e_ft256_rb_a.ppt
xapp_485/4bit_floorplans/top4_tx_3s250e_ft256_rt_a.ppt
xapp_485/4bit_floorplans/top4_tx_3s250e_tq144_a.ppt
xapp_485/4bit_floorplans/top4_tx_3s500e_fg320_tl_a.ppt
xapp_485/4bit_floorplans/top4_tx_3s500e_fg320_tr_a.ppt
xapp_485/4bit_floorplans/top4_tx_3s500e_ft256_rb_a.ppt
xapp_485/4bit_floorplans/top4_tx_3s500e_ft256_rt_a.ppt
xapp_485/4bit_verilog/
xapp_485/4bit_verilog/auto_phase_align_s3e.v
xapp_485/4bit_verilog/serdes_4b_1to7.v
xapp_485/4bit_verilog/serdes_4b_1to7_wrapper.v
xapp_485/4bit_verilog/top4_rx.v
xapp_485/4bit_vhdl/
xapp_485/4bit_vhdl/auto_phase_align_s3e.vhd
xapp_485/4bit_vhdl/serdes_4b_1to7.vhd
xapp_485/4bit_vhdl/serdes_4b_1to7_wrapper.vhd
xapp_485/4bit_vhdl/top4_rx.vhd
xapp_485/5bit_constraints/
xapp_485/5bit_constraints/top5_rx_3s100e_cp132_t_a.ucf
xapp_485/5bit_constraints/top5_rx_3s100e_vq100_t_a.ucf
xapp_485/5bit_constraints/top5_rx_3s1200e_fg320_tl_a.ucf
xapp_485/5bit_constraints/top5_rx_3s1200e_fg320_tr_a.ucf
xapp_485/5bit_constraints/top5_rx_3s1200e_ft256_tl_a.ucf
xapp_485/5bit_constraints/top5_rx_3s1200e_ft256_tr_a.ucf
xapp_485/5bit_constraints/top5_rx_3s1600e_fg320_tl_a.ucf
xapp_485/5bit_constraints/top5_rx_3s1600e_fg320_tr_a.ucf
xapp_485/5bit_constraints/top5_rx_3s1600e_fg484_tl_a.ucf
xapp_485/5bit_constraints/top5_rx_3s250e_cp132_t_a.ucf
xapp_485/5bit_constraints/top5_rx_3s250e_ft256_tl_a.ucf
xapp_485/5bit_constraints/top5_rx_3s250e_ft256_tr_a.ucf
xapp_485/5bit_constraints/top5_rx_3s250e_pq208_tl_a.ucf
xapp_485/5bit_constraints/top5_rx_3s250e_pq208_tr_a.ucf
xapp_485/5bit_constraints/top5_rx_3s250e_vq100_t_a.ucf
xapp_485/5bit_constraints/top5_rx_3s500e_cp132_t_a.ucf
xapp_485/5bit_constraints/top5_rx_3s500e_fg320_tl_a.ucf
xapp_485/5bit_constraints/top5_rx_3s500e_ft256_tl_a.ucf
xapp_485/5bit_constraints/top5_rx_3s500e_ft256_tr_a.ucf
xapp_485/5bit_constraints/top5_rx_3s500e_pq208_tl_a.ucf
xapp_485/5bit_constraints/top5_rx_3s500e_pq208_tr_a.ucf
xapp_485/5bit_floorplans/
xapp_485/5bit_floorplans/top5_rx_3s100e_vq100_t_a.ppt
xapp_485/5bit_floorplans/top5_rx_3s1200e_fg320_tl_a.ppt
xapp_485/5bit_floorplans/top5_rx_3s1200e_fg320_tr_a.ppt
xapp_485/5bit_floorplans/top5_rx_3s1200e_ft256_tl_a.ppt
xapp_485/5bit_floorplans/top5_rx_3s1200e_ft256_tr_a.ppt
xapp_485/5bit_floorplans/top5_rx_3s1600e_fg320_tl_a.ppt
xapp_485/5bit_floorplans/top5_rx_3s1600e_fg320_tr_a.ppt
xapp_485/5bit_floorplans/top5_rx_3s1600e_fg484_tl_a.ppt
xapp_485/5bit_floorplans/top5_rx_3s250e_cp132_t_a.ppt
xapp_485/5bit_floorplans/top5_rx_3s250e_ft256_tl_a.ppt
xapp_485/5bit_floorplans/top5_rx_3s250e_ft256_tr_a.ppt
xapp_485/5bit_floorplans/top5_rx_3s250e_vq100_t_a.ppt
xapp_485/5bit_floorplans/top5_rx_3s500e_cp132_t_a.ppt
xapp_485/5bit_floorplans/top5_rx_3s500e_fg320_tl_a.ppt
xapp_485/5bit_floorplans/top5_rx_3s500e_ft256_tl_a.ppt
xapp_485/5bit_floorplans/top5_rx_3s500e_ft256_tr_a.ppt
xapp_485/5bit_verilog/
xapp_485/5bit_verilog/auto_phase_align_s3e.v
xapp_485/5bit_verilog/serdes_5b_1to7.v
xapp_485/5bit_verilog/serdes_5b_1to7_wrapper.v
xapp_485/5bit_verilog/top5_rx.v
xapp_485/5bit_vhdl/
xapp_485/5bit_vhdl/auto_phase_align_s3e.vhd
xapp_485/5bit_vhdl/serdes_5b_1to7.vhd
xapp_485/5bit_vhdl/serdes_5b_1to7_wrapper.vhd
xapp_485/5bit_vhdl/top5_rx.vhd
xapp_485/receiver_floorplan.ppt
xapp_485/xapp485_calculations.xls
xapp_485/xapp_485_readme.txt