压缩包 : 95302918alterafpga_cplddesignbasic.rar 列表
光盘使用说明.doc
Example-b8-3\示例说明.doc
Example-b8-1\示例说明.doc
Example-b8-2\示例说明.doc
Example-b8-4\示例说明.doc
Example-b8-5\示例说明.doc
Example-b8-6\示例说明.doc
Example-b4-2\示例说明.doc
Example-b4-1\示例说明.doc
Example-b3-1\示例说明.doc
Example-b8-1\Altera_lib_files\220model.txt
Example-b8-2\Altera_lib_files\220model.txt
Example-b8-1\Altera_lib_files\altera_mf.txt
Example-b8-2\Altera_lib_files\altera_mf.txt
Example-b8-1\source\dpram8x32_waveforms.html
Example-b8-2\source\dpram8x32_waveforms.html
Example-b4-2\Solution\IP_ENC\ENC.html
Example-b3-1\uart_regs\core\myfifo_10_waveforms.html
Example-b3-1\uart_regs\core\myfifo_8_waveforms.html
Example-b8-6\Synplify_Pro\rev_2\stderr.log
Example-b8-6\Synplify_Pro\rev_3\stderr.log
Example-b8-6\Synplify_Pro\rev_2\stdout.log
Example-b8-6\Synplify_Pro\rev_3\stdout.log
Example-b3-1\uart_regs\dev\cmp_state.ini
Example-b8-1\pll_ram\cmp_state.ini
Example-b8-2\pll_ram\cmp_state.ini
Example-b8-1\timing_sim\work\exp\verilog.asm
Example-b8-2\timing_sim\work\exp\verilog.asm
Example-b8-1\timing_sim\work\carry\verilog.asm
Example-b8-1\timing_sim\work\cascade\verilog.asm
Example-b8-1\timing_sim\work\global\verilog.asm
Example-b8-2\timing_sim\work\carry\verilog.asm
Example-b8-2\timing_sim\work\cascade\verilog.asm
Example-b8-2\timing_sim\work\global\verilog.asm
Example-b8-1\timing_sim\work\lcell\verilog.asm
Example-b8-2\timing_sim\work\lcell\verilog.asm
Example-b8-1\timing_sim\work\@p@r@i@m_@d@f@f@e\verilog.asm
Example-b8-2\timing_sim\work\@p@r@i@m_@d@f@f@e\verilog.asm
Example-b8-1\timing_sim\work\carry_sum\verilog.asm
Example-b8-2\timing_sim\work\carry_sum\verilog.asm
Example-b8-1\timing_sim\work\and1\verilog.asm
Example-b8-2\timing_sim\work\and1\verilog.asm
Example-b8-1\timing_sim\work\io_buf_opdrn\verilog.asm
Example-b8-2\timing_sim\work\io_buf_opdrn\verilog.asm
Example-b8-1\timing_sim\work\io_buf_tri\verilog.asm
Example-b8-2\timing_sim\work\io_buf_tri\verilog.asm
Example-b8-3\work\counter\verilog.asm
Example-b8-1\timing_sim\work\nmux21\verilog.asm
Example-b8-1\timing_sim\work\b5mux21\verilog.asm
Example-b8-1\timing_sim\work\bmux21\verilog.asm
Example-b8-2\timing_sim\work\b5mux21\verilog.asm
Example-b8-2\timing_sim\work\bmux21\verilog.asm
Example-b8-1\timing_sim\work\b17mux21\verilog.asm
Example-b8-2\timing_sim\work\b17mux21\verilog.asm
Example-b8-1\timing_sim\work\stratix_crcblock\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_crcblock\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_crcblock\verilog.asm
Example-b8-1\timing_sim\work\dffp\verilog.asm
Example-b8-2\timing_sim\work\dffp\verilog.asm
Example-b8-1\timing_sim\work\pll_reg\verilog.asm
Example-b8-1\timing_sim\work\@m@f_pll_reg\verilog.asm
Example-b8-2\timing_sim\work\@m@f_pll_reg\verilog.asm
Example-b8-1\timing_sim\work\lpm_constant\verilog.asm
Example-b8-2\timing_sim\work\lpm_constant\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_ram_clear\verilog.asm
Example-b8-1\timing_sim\work\stratix_ram_clear\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_ram_clear\verilog.asm
Example-b8-5\demo_project\work\test_counter\verilog.asm
Example-b8-1\timing_sim\work\lpm_outpad\verilog.asm
Example-b8-1\timing_sim\work\lpm_inpad\verilog.asm
Example-b8-1\timing_sim\work\lpm_inv\verilog.asm
Example-b8-1\timing_sim\work\oper_decoder\verilog.asm
Example-b8-1\timing_sim\work\and16\verilog.asm
Example-b8-2\timing_sim\work\and16\verilog.asm
Example-b8-1\timing_sim\work\mux21\verilog.asm
Example-b8-1\timing_sim\work\stratix_jtag\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_jtag\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_jtag\verilog.asm
Example-b8-1\timing_sim\work\arm_n_cntr\verilog.asm
Example-b8-2\timing_sim\work\arm_n_cntr\verilog.asm
Example-b8-1\timing_sim\work\oper_mux\verilog.asm
Example-b8-5\demo_project\work\counter\verilog.asm
Example-b8-1\timing_sim\work\n_cntr\verilog.asm
Example-b8-1\timing_sim\work\m_cntr\verilog.asm
Example-b8-1\timing_sim\work\stx_n_cntr\verilog.asm
Example-b8-1\timing_sim\work\lpm_bipad\verilog.asm
Example-b8-2\timing_sim\work\lpm_bipad\verilog.asm
Example-b8-1\timing_sim\work\arm_m_cntr\verilog.asm
Example-b8-2\timing_sim\work\arm_m_cntr\verilog.asm
Example-b8-1\func_sim\work\pll_ram\verilog.asm
Example-b8-2\func_sim\work\pll_ram\verilog.asm
Example-b8-1\timing_sim\work\latch\verilog.asm
Example-b8-2\timing_sim\work\latch\verilog.asm
Example-b8-1\timing_sim\work\stx_m_cntr\verilog.asm
Example-b8-1\timing_sim\work\mux41\verilog.asm
Example-b8-1\timing_sim\work\lpm_abs\verilog.asm
Example-b8-2\timing_sim\work\lpm_abs\verilog.asm
Example-b8-1\timing_sim\work\oper_selector\verilog.asm
Example-b8-1\timing_sim\work\tri_bus\verilog.asm
Example-b8-1\timing_sim\work\a_graycounter\verilog.asm
Example-b8-2\timing_sim\work\a_graycounter\verilog.asm
Example-b8-1\func_sim\work\dpram8x32\verilog.asm
Example-b8-2\func_sim\work\dpram8x32\verilog.asm
Example-b8-1\timing_sim\work\dffe\verilog.asm
Example-b8-2\timing_sim\work\dffe\verilog.asm
Example-b8-1\func_sim\work\pll_ram_tb\verilog.asm
Example-b8-1\timing_sim\work\pll_ram_tb\verilog.asm
Example-b8-2\func_sim\work\pll_ram_tb\verilog.asm
Example-b8-1\timing_sim\work\oper_mult\verilog.asm
Example-b8-1\timing_sim\work\oper_rotate_left\verilog.asm
Example-b8-1\timing_sim\work\oper_rotate_right\verilog.asm
Example-b8-1\timing_sim\work\lpm_bustri\verilog.asm
Example-b8-2\timing_sim\work\lpm_bustri\verilog.asm
Example-b8-1\timing_sim\work\oper_add\verilog.asm
Example-b8-1\timing_sim\work\lpm_or\verilog.asm
Example-b8-1\timing_sim\work\arm_scale_cntr\verilog.asm
Example-b8-2\timing_sim\work\arm_scale_cntr\verilog.asm
Example-b8-1\timing_sim\work\lpm_xor\verilog.asm
Example-b8-1\timing_sim\work\lpm_and\verilog.asm
Example-b8-2\timing_sim\work\lpm_and\verilog.asm
Example-b8-1\timing_sim\work\altddio_bidir\verilog.asm
Example-b8-2\timing_sim\work\altddio_bidir\verilog.asm
Example-b8-1\timing_sim\work\lpm_fifo_dc_dffpipe\verilog.asm
Example-b8-1\timing_sim\work\dcfifo_dffpipe\verilog.asm
Example-b8-2\timing_sim\work\dcfifo_dffpipe\verilog.asm
Example-b8-1\timing_sim\work\oper_bus_mux\verilog.asm
Example-b8-1\func_sim\work\pllx2\verilog.asm
Example-b8-2\func_sim\work\pllx2\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_lvds_tx_out_block\verilog.asm
Example-b8-1\timing_sim\work\stratix_lvds_tx_out_block\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_lvds_tx_out_block\verilog.asm
Example-b8-1\timing_sim\work\scale_cntr\verilog.asm
Example-b8-1\timing_sim\work\stx_scale_cntr\verilog.asm
Example-b8-1\timing_sim\work\stratix_lcell\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_lcell\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_lcell\verilog.asm
Example-b8-1\timing_sim\work\lpm_latch\verilog.asm
Example-b8-1\timing_sim\work\oper_left_shift\verilog.asm
Example-b8-1\timing_sim\work\stratixii_tx_outclk\verilog.asm
Example-b8-1\timing_sim\work\@l@p@m_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n\verilog.asm
Example-b8-2\timing_sim\work\@l@p@m_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n\verilog.asm
Example-b8-1\timing_sim\work\oper_div\verilog.asm
Example-b8-1\timing_sim\work\oper_mod\verilog.asm
Example-b8-1\timing_sim\work\oper_less_than\verilog.asm
Example-b8-1\timing_sim\work\oper_right_shift\verilog.asm
Example-b8-1\timing_sim\work\lpm_fifo_dc\verilog.asm
Example-b8-1\timing_sim\work\lpm_decode\verilog.asm
Example-b8-2\timing_sim\work\lpm_decode\verilog.asm
Example-b8-1\timing_sim\work\hssi_tx\verilog.asm
Example-b8-2\timing_sim\work\hssi_tx\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_lvds_rx_parallel_register\verilog.asm
Example-b8-1\timing_sim\work\stratix_lvds_rx_parallel_register\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_lvds_rx_parallel_register\verilog.asm
Example-b8-1\timing_sim\work\altshift_taps\verilog.asm
Example-b8-2\timing_sim\work\altshift_taps\verilog.asm
Example-b8-1\timing_sim\work\dcfifo_fefifo\verilog.asm
Example-b8-2\timing_sim\work\dcfifo_fefifo\verilog.asm
Example-b8-1\timing_sim\work\oper_addsub\verilog.asm
Example-b8-1\timing_sim\work\lpm_mux\verilog.asm
Example-b8-1\timing_sim\work\stratix_io_register\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_io_register\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_io_register\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_lvds_tx_parallel_register\verilog.asm
Example-b8-1\timing_sim\work\stratix_lvds_tx_parallel_register\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_lvds_tx_parallel_register\verilog.asm
Example-b8-1\timing_sim\work\stratix_lvds_rx\verilog.asm
Example-b8-1\timing_sim\work\@m@f_ram7x20_syn\verilog.asm
Example-b8-2\timing_sim\work\@m@f_ram7x20_syn\verilog.asm
Example-b8-1\timing_sim\work\hssi_fifo\verilog.asm
Example-b8-2\timing_sim\work\hssi_fifo\verilog.asm
Example-b8-1\timing_sim\work\stratix_lcell_register\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_lcell_register\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_lcell_register\verilog.asm
Example-b8-1\timing_sim\work\dcfifo\verilog.asm
Example-b8-2\timing_sim\work\dcfifo\verilog.asm
Example-b8-1\timing_sim\work\lpm_fifo_dc_fefifo\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_lvds_receiver\verilog.asm
Example-b8-1\timing_sim\work\stratix_lvds_receiver\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_lvds_receiver\verilog.asm
Example-b8-1\timing_sim\work\stratix_lvds_transmitter\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_lvds_transmitter\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_lvds_transmitter\verilog.asm
Example-b8-1\timing_sim\work\lpm_ff\verilog.asm
Example-b8-2\timing_sim\work\lpm_ff\verilog.asm
Example-b8-1\timing_sim\work\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm
Example-b8-2\timing_sim\work\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm
Example-b8-1\timing_sim\work\hssi_rx\verilog.asm
Example-b8-2\timing_sim\work\hssi_rx\verilog.asm
Example-b8-1\timing_sim\work\altddio_in\verilog.asm
Example-b8-2\timing_sim\work\altddio_in\verilog.asm
Example-b8-1\timing_sim\work\lpm_shiftreg\verilog.asm
Example-b8-1\timing_sim\work\stratix_io\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_io\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_io\verilog.asm
Example-b8-1\timing_sim\work\lpm_compare\verilog.asm
Example-b8-2\timing_sim\work\lpm_compare\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_asynch_io\verilog.asm
Example-b8-1\timing_sim\work\stratix_asynch_io\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_asynch_io\verilog.asm
Example-b8-1\timing_sim\work\altsqrt\verilog.asm
Example-b8-2\timing_sim\work\altsqrt\verilog.asm
Example-b8-1\timing_sim\work\stratix_rublock\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_rublock\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_rublock\verilog.asm
Example-b8-1\timing_sim\work\@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm
Example-b8-2\timing_sim\work\@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm
Example-b8-1\timing_sim\work\altddio_out\verilog.asm
Example-b8-2\timing_sim\work\altddio_out\verilog.asm
Example-b8-1\timing_sim\work\lpm_rom\verilog.asm
Example-b8-1\timing_sim\work\alt_exc_dpram\verilog.asm
Example-b8-2\timing_sim\work\alt_exc_dpram\verilog.asm
Example-b8-1\timing_sim\work\lpm_counter\verilog.asm
Example-b8-2\timing_sim\work\lpm_counter\verilog.asm
Example-b8-1\timing_sim\work\lpm_ram_io\verilog.asm
Example-b8-1\timing_sim\work\stratix_dll\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_dll\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_dll\verilog.asm
Example-b8-1\timing_sim\work\stratix_mac_mult\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_mac_mult\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_mac_mult\verilog.asm
Example-b8-1\timing_sim\work\lpm_ram_dq\verilog.asm
Example-b8-1\timing_sim\work\lpm_mult\verilog.asm
Example-b8-1\timing_sim\work\lpm_divide\verilog.asm
Example-b8-2\timing_sim\work\lpm_divide\verilog.asm
Example-b8-1\timing_sim\work\parallel_add\verilog.asm
Example-b8-1\timing_sim\work\lpm_clshift\verilog.asm
Example-b8-2\timing_sim\work\lpm_clshift\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_mac_mult_internal\verilog.asm
Example-b8-1\timing_sim\work\stratix_mac_mult_internal\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_mac_mult_internal\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_mac_register\verilog.asm
Example-b8-1\timing_sim\work\stratix_mac_register\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_mac_register\verilog.asm
Example-b8-1\timing_sim\work\altaccumulate\verilog.asm
Example-b8-2\timing_sim\work\altaccumulate\verilog.asm
Example-b8-1\timing_sim\work\lpm_add_sub\verilog.asm
Example-b8-2\timing_sim\work\lpm_add_sub\verilog.asm
Example-b8-1\timing_sim\work\lpm_ram_dp\verilog.asm
Example-b8-1\timing_sim\work\hssi_pll\verilog.asm
Example-b8-2\timing_sim\work\hssi_pll\verilog.asm
Example-b8-1\timing_sim\work\altdpram\verilog.asm
Example-b8-2\timing_sim\work\altdpram\verilog.asm
Example-b8-1\timing_sim\work\lpm_fifo\verilog.asm
Example-b8-2\timing_sim\work\lpm_fifo\verilog.asm
Example-b8-1\timing_sim\work\dcfifo_sync\verilog.asm
Example-b8-2\timing_sim\work\dcfifo_sync\verilog.asm
Example-b8-1\timing_sim\work\dcfifo_async\verilog.asm
Example-b8-2\timing_sim\work\dcfifo_async\verilog.asm
Example-b8-1\timing_sim\work\scfifo\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_asynch_lcell\verilog.asm
Example-b8-1\timing_sim\work\stratix_asynch_lcell\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_asynch_lcell\verilog.asm
Example-b8-1\timing_sim\work\lpm_fifo_dc_async\verilog.asm
Example-b8-1\timing_sim\work\stratix_mac_out\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_mac_out\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_mac_out\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_mac_out_internal\verilog.asm
Example-b8-1\timing_sim\work\stratix_mac_out_internal\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_mac_out_internal\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_ram_register\verilog.asm
Example-b8-1\timing_sim\work\stratix_ram_register\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_ram_register\verilog.asm
Example-b8-1\timing_sim\work\stratixii_lvds_rx\verilog.asm
Example-b8-1\timing_sim\work\stratixgx_dpa_lvds_rx\verilog.asm
Example-b8-1\timing_sim\work\altcdr_tx\verilog.asm
Example-b8-2\timing_sim\work\altcdr_tx\verilog.asm
Example-b8-1\timing_sim\work\altcdr_rx\verilog.asm
Example-b8-2\timing_sim\work\altcdr_rx\verilog.asm
Example-b8-1\timing_sim\work\alt3pram\verilog.asm
Example-b8-2\timing_sim\work\alt3pram\verilog.asm
Example-b8-1\timing_sim\work\altclklock\verilog.asm
Example-b8-2\timing_sim\work\altclklock\verilog.asm
Example-b8-1\timing_sim\work\altfp_mult\verilog.asm
Example-b8-2\timing_sim\work\altfp_mult\verilog.asm
Example-b8-1\timing_sim\work\stratix_ram_block\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_ram_block\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_ram_block\verilog.asm
Example-b8-1\timing_sim\work\pll_ram\verilog.asm
Example-b8-1\timing_sim\work\altpll\verilog.asm
Example-b8-2\timing_sim\work\altpll\verilog.asm
Example-b8-1\timing_sim\work\altlvds_tx\verilog.asm
Example-b8-2\timing_sim\work\altlvds_tx\verilog.asm
Example-b8-1\timing_sim\work\altlvds_rx\verilog.asm
Example-b8-2\timing_sim\work\altlvds_rx\verilog.asm
Example-b8-1\timing_sim\work\altqpram\verilog.asm
Example-b8-2\timing_sim\work\altqpram\verilog.asm
Example-b8-1\timing_sim\work\altsyncram\verilog.asm
Example-b8-2\timing_sim\work\altsyncram\verilog.asm
Example-b8-1\timing_sim\work\alt_exc_upcore\verilog.asm
Example-b8-2\timing_sim\work\alt_exc_upcore\verilog.asm
Example-b8-1\timing_sim\work\altcam\verilog.asm
Example-b8-2\timing_sim\work\altcam\verilog.asm
Example-b8-1\timing_sim\work\altmult_accum\verilog.asm
Example-b8-2\timing_sim\work\altmult_accum\verilog.asm
Example-b8-1\timing_sim\work\@m@f_stratixii_pll\verilog.asm
Example-b8-2\timing_sim\work\@m@f_stratixii_pll\verilog.asm
Example-b8-1\timing_sim\work\stratix_pll\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_pll\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_pll\verilog.asm
Example-b8-1\timing_sim\work\@m@f_stratix_pll\verilog.asm
Example-b8-2\timing_sim\work\@m@f_stratix_pll\verilog.asm
Example-b8-1\timing_sim\work\altmult_add\verilog.asm
Example-b8-2\timing_sim\work\altmult_add\verilog.asm
Example-b8-1\timing_sim\work\hcstratix_ram_internal\verilog.asm
Example-b8-2\timing_sim\work\hcstratix_ram_internal\verilog.asm
Example-b8-1\timing_sim\work\stratix_ram_internal\verilog.asm
Example-b8-1\func_sim\wave.bmp
Example-b8-2\func_sim\wave.bmp
Example-b8-1\timing_sim\-help
Example-b8-2\timing_sim\-help
Example-b8-1\timing_sim\work\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s
Example-b8-2\timing_sim\work\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s
Example-b8-1\timing_sim\work\@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s
Example-b8-2\timing_sim\work\@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s
Example-b8-1\timing_sim\work\@l@p@m_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n
Example-b8-2\timing_sim\work\@l@p@m_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n
Example-b8-1\timing_sim\work\@m@f_pll_reg
Example-b8-2\timing_sim\work\@m@f_pll_reg
Example-b8-1\timing_sim\work\@m@f_ram7x20_syn
Example-b8-2\timing_sim\work\@m@f_ram7x20_syn
Example-b8-1\timing_sim\work\@m@f_stratix_pll
Example-b8-2\timing_sim\work\@m@f_stratix_pll
Example-b8-1\timing_sim\work\@m@f_stratixii_pll
Example-b8-2\timing_sim\work\@m@f_stratixii_pll
Example-b8-1\timing_sim\work\@p@r@i@m_@d@f@f@e
Example-b8-2\timing_sim\work\@p@r@i@m_@d@f@f@e
Example-b8-3\work\_info
Example-b8-5\demo_project\work\_info
Example-b8-1\func_sim\work\_info
Example-b8-2\func_sim\work\_info
Example-b8-1\timing_sim\work\_info
Example-b8-1\timing_sim\work\a_graycounter
Example-b8-2\timing_sim\work\a_graycounter
Example-b8-1\timing_sim\work\alt_exc_dpram
Example-b8-2\timing_sim\work\alt_exc_dpram
Example-b8-1\timing_sim\work\alt_exc_upcore
Example-b8-2\timing_sim\work\alt_exc_upcore
Example-b8-1\timing_sim\work\alt3pram
Example-b8-2\timing_sim\work\alt3pram
Example-b8-1\timing_sim\work\altaccumulate
Example-b8-2\timing_sim\work\altaccumulate
Example-b8-1\timing_sim\work\altcam
Example-b8-2\timing_sim\work\altcam
Example-b8-1\timing_sim\work\altcdr_rx
Example-b8-2\timing_sim\work\altcdr_rx
Example-b8-1\timing_sim\work\altcdr_tx
Example-b8-2\timing_sim\work\altcdr_tx
Example-b8-1\timing_sim\work\altclklock
Example-b8-2\timing_sim\work\altclklock
Example-b8-1\timing_sim\work\altddio_bidir
Example-b8-2\timing_sim\work\altddio_bidir
Example-b8-1\timing_sim\work\altddio_in
Example-b8-2\timing_sim\work\altddio_in
Example-b8-1\timing_sim\work\altddio_out
Example-b8-2\timing_sim\work\altddio_out
Example-b8-1\timing_sim\work\altdpram
Example-b8-2\timing_sim\work\altdpram
Example-b8-1\Altera_lib_files
Example-b8-2\Altera_lib_files
Example-b8-1\timing_sim\work\altfp_mult
Example-b8-2\timing_sim\work\altfp_mult
Example-b8-1\timing_sim\work\altlvds_rx
Example-b8-2\timing_sim\work\altlvds_rx
Example-b8-1\timing_sim\work\altlvds_tx
Example-b8-2\timing_sim\work\altlvds_tx
Example-b8-1\timing_sim\work\altmult_accum
Example-b8-2\timing_sim\work\altmult_accum
Example-b8-1\timing_sim\work\altmult_add
Example-b8-2\timing_sim\work\altmult_add
Example-b8-1\timing_sim\work\altpll
Example-b8-2\timing_sim\work\altpll
Example-b8-1\timing_sim\work\altqpram
Example-b8-2\timing_sim\work\altqpram
Example-b8-1\timing_sim\work\altshift_taps
Example-b8-2\timing_sim\work\altshift_taps
Example-b8-1\timing_sim\work\altsqrt
Example-b8-2\timing_sim\work\altsqrt
Example-b8-1\timing_sim\work\altsyncram
Example-b8-2\timing_sim\work\altsyncram
Example-b8-1\timing_sim\work\and1
Example-b8-2\timing_sim\work\and1
Example-b8-1\timing_sim\work\and16
Example-b8-2\timing_sim\work\and16
Example-b8-1\timing_sim\work\arm_m_cntr
Example-b8-2\timing_sim\work\arm_m_cntr
Example-b8-1\timing_sim\work\arm_n_cntr
Example-b8-2\timing_sim\work\arm_n_cntr
Example-b8-1\timing_sim\work\arm_scale_cntr
Example-b8-2\timing_sim\work\arm_scale_cntr
Example-b4-2\Solution\IP_ENC\hw\build\b0iwe
Example-b8-1\timing_sim\work\b17mux21
Example-b8-2\timing_sim\work\b17mux21
Example-b8-1\timing_sim\work\b5mux21
Example-b8-2\timing_sim\work\b5mux21
Example-b8-1\timing_sim\work\bmux21
Example-b8-2\timing_sim\work\bmux21
Example-b4-2\Solution\IP_ENC\hw\build
Example-b8-1\timing_sim\work\carry
Example-b8-2\timing_sim\work\carry
Example-b8-1\timing_sim\work\carry_sum
Example-b8-2\timing_sim\work\carry_sum
Example-b8-1\timing_sim\work\cascade
Example-b8-2\timing_sim\work\cascade
Example-b8-3\work\counter
Example-b8-5\demo_project\work\counter
Example-b3-1\uart_regs\core\db
Example-b3-1\uart_regs\core
Example-b3-1\uart_regs\src\sch\db
Example-b8-1\pll_ram\db
Example-b8-2\pll_ram\db
Example-b8-1\timing_sim\work\dcfifo
Example-b8-2\timing_sim\work\dcfifo
Example-b8-1\timing_sim\work\dcfifo_async
Example-b8-2\timing_sim\work\dcfifo_async
Example-b8-1\timing_sim\work\dcfifo_dffpipe
Example-b8-2\timing_sim\work\dcfifo_dffpipe
Example-b8-1\timing_sim\work\dcfifo_fefifo
Example-b8-2\timing_sim\work\dcfifo_fefifo
Example-b8-1\timing_sim\work\dcfifo_sync
Example-b8-2\timing_sim\work\dcfifo_sync
Example-b8-5\demo_project
Example-b8-1\timing_sim\work\dffe
Example-b8-2\timing_sim\work\dffe
Example-b8-1\timing_sim\work\dffp
Example-b8-2\timing_sim\work\dffp
Example-b8-1\func_sim\work\dpram8x32
Example-b8-2\func_sim\work\dpram8x32
Example-b4-2\Solution\IP_ENC\ENC_run_modelsim_verilog
Example-b4-2\Solution\IP_ENC\ENC_run_modelsim_vhdl
Example-b3-1\uart_regs\sim\funcsim
Example-b3-1\uart_regs\sim\parsim
Example-b3-1\uart_regs\src\sch\sch_exam.bdf
Example-b3-1\uart_regs\src\sch\lpm_mux0.bsf
Example-b3-1\uart_regs\src\sch
Example-b3-1\uart_regs\sim
Example-b3-1\uart_regs\src
Example-b3-1\uart_regs\dev\db\uart_regs_hier_info
Example-b3-1\uart_regs\dev\db\uart_regs_syn_hier_info
Example-b3-1\uart_regs\dev\chip_editor.acv
Example-b3-1\uart_regs\dev\db\uart_regs(0).cnf.cdb
Example-b3-1\uart_regs\dev\db\uart_regs(1).cnf.cdb
Example-b3-1\uart_regs\dev\db\uart_regs(10).cnf.cdb
Example-b3-1\uart_regs\dev\db\uart_regs(11).cnf.cdb
Example-b3-1\uart_regs\dev\db\uart_regs(12).cnf.cdb
Example-b3-1\uart_regs\dev\db\uart_regs(13).cnf.cdb
Example-b3-1\uart_regs\dev\db\uart_regs(14).cnf.cdb
Example-b3-1\uart_regs\dev\db\uart_regs(15).cnf.cdb
Example-b3-1\uart_regs\dev\db\uart_regs(16).cnf.cdb
Example-b3-1\uart_regs\dev\db\uart_regs(17).cnf.cdb
Example-b3-1\uart_regs\dev\db\uart_regs(18).cnf.cdb
Example-b3-1\uart_regs\dev\db\uart_regs(19).cnf.cdb
Example-b3-1\uart_regs\dev\db\uart_regs(2).cnf.cdb
Example-b3-1\uart_regs\dev\db\uart_regs(20).cnf.cdb
Example-b3-1\uart_regs\dev\db\uart_regs(21).cnf.cdb
Example-b3-1\uart_regs\dev\db\uart_regs(3).cnf.cdb
Example-b3-1\uart_regs\dev\db\uart_regs(4).cnf.cdb
Example-b3-1\uart_regs\dev\db\uart_regs(5).cnf.cdb
Example-b3-1\uart_regs\dev\db\uart_regs(6).cnf.cdb
Example-b3-1\uart_regs\dev\db\uart_regs(7).cnf.cdb
Example-b3-1\uart_regs\dev\db\uart_regs(8).cnf.cdb
Example-b3-1\uart_regs\dev\db\uart_regs(9).cnf.cdb
Example-b3-1\uart_regs\dev\db\uart_regs.cmp.cdb
Example-b3-1\uart_regs\dev\db\uart_regs.fnsim.cdb
Example-b3-1\uart_regs\dev\db\uart_regs.map.cdb
Example-b3-1\uart_regs\dev\db\uart_regs.rtlv_sg.cdb
Example-b3-1\uart_regs\dev\db\uart_regs.rtlv_sg_swap.cdb
Example-b3-1\uart_regs\dev\db\uart_regs.sgdiff.cdb
Example-b3-1\uart_regs\dev\db\uart_regs.signalprobe.cdb
Example-b3-1\uart_regs\dev\db
Example-b3-1\uart_regs\dev\sim.cfg
Example-b3-1\uart_regs\dev\db\uart_regs.db_info
Example-b3-1\uart_regs\dev\uart_regs.done
Example-b3-1\uart_regs\dev\uart_regs.fit.eqn
Example-b3-1\uart_regs\dev\uart_regs.map.eqn
Example-b3-1\uart_regs\dev\db\uart_regs.fld
Example-b3-1\uart_regs\dev\uart_regs.fld
Example-b3-1\uart_regs\dev\db\uart_regs(0).cnf.hdb
Example-b3-1\uart_regs\dev\db\uart_regs(1).cnf.hdb
Example-b3-1\uart_regs\dev\db\uart_regs(10).cnf.hdb
Example-b3-1\uart_regs\dev\db\uart_regs(11).cnf.hdb
Example-b3-1\uart_regs\dev\db\uart_regs(12).cnf.hdb
Example-b3-1\uart_regs\dev\db\uart_regs(13).cnf.hdb
Example-b3-1\uart_regs\dev\db\uart_regs(14).cnf.hdb
Example-b3-1\uart_regs\dev\db\uart_regs(15).cnf.hdb
Example-b3-1\uart_regs\dev\db\uart_regs(16).cnf.hdb
Example-b3-1\uart_regs\dev\db\uart_regs(17).cnf.hdb
Example-b3-1\uart_regs\dev\db\uart_regs(18).cnf.hdb
Example-b3-1\uart_regs\dev\db\uart_regs(19).cnf.hdb
Example-b3-1\uart_regs\dev\db\uart_regs(2).cnf.hdb
Example-b3-1\uart_regs\dev\db\uart_regs(20).cnf.hdb
Example-b3-1\uart_regs\dev\db\uart_regs(21).cnf.hdb
Example-b3-1\uart_regs\dev\db\uart_regs(3).cnf.hdb
Example-b3-1\uart_regs\dev\db\uart_regs(4).cnf.hdb
Example-b3-1\uart_regs\dev\db\uart_regs(5).cnf.hdb
Example-b3-1\uart_regs\dev\db\uart_regs(6).cnf.hdb
Example-b3-1\uart_regs\dev\db\uart_regs(7).cnf.hdb
Example-b3-1\uart_regs\dev\db\uart_regs(8).cnf.hdb
Example-b3-1\uart_regs\dev\db\uart_regs(9).cnf.hdb
Example-b3-1\uart_regs\dev\db\uart_regs.cmp.hdb
Example-b3-1\uart_regs\dev\db\uart_regs.fnsim.hdb
Example-b3-1\uart_regs\dev\db\uart_regs.map.hdb
Example-b3-1\uart_regs\dev\db\uart_regs.pre_map.hdb
Example-b3-1\uart_regs\dev\db\uart_regs.project.hdb
Example-b3-1\uart_regs\dev\db\uart_regs.rtlv.hdb
Example-b3-1\uart_regs\dev\db\uart_regs.sgdiff.hdb
Example-b3-1\uart_regs\dev\db\uart_regs.sim.hdb
Example-b3-1\uart_regs\dev\db\uart_regs.hif
Example-b3-1\uart_regs\dev\db\uart_regs.icc
Example-b3-1\uart_regs\dev\uart_regs.pin
Example-b3-1\uart_regs\dev\uart_regs.pof
Example-b3-1\uart_regs\dev\db\uart_regs.asm.qmsg
Example-b3-1\uart_regs\dev\db\uart_regs.csf.qmsg
Example-b3-1\uart_regs\dev\db\uart_regs.fit.qmsg
Example-b3-1\uart_regs\dev\db\uart_regs.map.qmsg
Example-b3-1\uart_regs\dev\db\uart_regs.rpp.qmsg
Example-b3-1\uart_regs\dev\db\uart_regs.sim.qmsg
Example-b3-1\uart_regs\dev\db\uart_regs.tan.qmsg
Example-b3-1\uart_regs\dev\uart_regs.qpf
Example-b3-1\uart_regs\dev\db\uart_regs_cmp.qrpt
Example-b3-1\uart_regs\dev\db\uart_regs_sim.qrpt
Example-b3-1\uart_regs\dev\uart_regs.qsf
Example-b3-1\uart_regs\dev\uart_regs.qws
Example-b3-1\uart_regs\dev\uart_regs.rbf
Example-b3-1\uart_regs\dev\db\uart_regs.cmp.rdb
Example-b3-1\uart_regs\dev\db\uart_regs.sim.rdb
Example-b3-1\uart_regs\dev\uart_regs.asm.rpt
Example-b3-1\uart_regs\dev\uart_regs.fit.rpt
Example-b3-1\uart_regs\dev\uart_regs.flow.rpt
Example-b3-1\uart_regs\dev\uart_regs.map.rpt
Example-b3-1\uart_regs\dev\uart_regs.sim.rpt
Example-b3-1\uart_regs\dev\uart_regs.tan.rpt
Example-b3-1\uart_regs\dev\db\uart_regs.rtlv_rvd.rvd
Example-b3-1\uart_regs\dev\db\uart_regs.uart_regs.sld_design_entry.sci
Example-b3-1\uart_regs\dev\uart_regs.sof
Example-b3-1\uart_regs\dev\uart_regs.tan.summary
Example-b3-1\uart_regs\dev\db\a_dpfifo_4nl.tdf
Example-b3-1\uart_regs\dev\db\a_dpfifo_rll.tdf
Example-b3-1\uart_regs\dev\db\a_fefifo_qve.tdf
Example-b3-1\uart_regs\dev\db\add_sub_1jh.tdf
Example-b3-1\uart_regs\dev\db\add_sub_dhh.tdf
Example-b3-1\uart_regs\dev\db\add_sub_ehh.tdf
Example-b3-1\uart_regs\dev\db\add_sub_fhh.tdf
Example-b3-1\uart_regs\dev\db\add_sub_ihh.tdf
Example-b3-1\uart_regs\dev\db\add_sub_rih.tdf
Example-b3-1\uart_regs\dev\db\altsyncram_apb1.tdf
Example-b3-1\uart_regs\dev\db\altsyncram_mmb1.tdf
Example-b3-1\uart_regs\dev\db\dpram_81k.tdf
Example-b3-1\uart_regs\dev\db\dpram_h2k.tdf
Example-b3-1\uart_regs\dev\db\scfifo_eaq.tdf
Example-b3-1\uart_regs\dev\db\scfifo_nbq.tdf
Example-b3-1\uart_regs\dev
Example-b3-1\uart_regs\src\sch\lpm_mux0.v
Example-b3-1\uart_regs\src\sch\lpm_mux0_bb.v
Example-b3-1\uart_regs\core\myfifo_10.v
Example-b3-1\uart_regs\core\myfifo_10_bb.v
Example-b3-1\uart_regs\core\myfifo_8.v
Example-b3-1\uart_regs\core\myfifo_8_bb.v
Example-b3-1\uart_regs\src\seriesPort.v
Example-b3-1\uart_regs\src\uart_defines.v
Example-b3-1\uart_regs\src\uart_receiver.v
Example-b3-1\uart_regs\src\uart_regs.v
Example-b3-1\uart_regs\src\uart_transmitter.v
Example-b3-1\uart_regs\dev\db\uart_regs-sim.vwf
Example-b3-1\uart_regs\sim\funcsim\uart_regs_h.vwf
Example-b3-1\uart_regs\sim\funcsim\uart_regs_pre.vwf
Example-b3-1\uart_regs\core\myfifo_10_wave0.jpg
Example-b3-1\uart_regs\core\myfifo_8_wave0.jpg
Example-b3-1\uart_regs
Example-b3-1
Example-b4-1
Example-b4-2
Example-b8-3
Example-b8-4
Example-b8-5
Example-b8-6
Example-b8-1\timing_sim\work\exp
Example-b8-2\timing_sim\work\exp
Example-b8-2\func_sim
Example-b8-1\timing_sim\work\global
Example-b8-2\timing_sim\work\global
Example-b8-1\timing_sim\work\hcstratix_asynch_io
Example-b8-2\timing_sim\work\hcstratix_asynch_io
Example-b8-1\timing_sim\work\hcstratix_asynch_lcell
Example-b8-2\timing_sim\work\hcstratix_asynch_lcell
Example-b8-1\timing_sim\work\hcstratix_crcblock
Example-b8-2\timing_sim\work\hcstratix_crcblock
Example-b8-1\timing_sim\work\hcstratix_dll
Example-b8-2\timing_sim\work\hcstratix_dll
Example-b8-1\timing_sim\work\hcstratix_io
Example-b8-2\timing_sim\work\hcstratix_io
Example-b8-1\timing_sim\work\hcstratix_io_register
Example-b8-2\timing_sim\work\hcstratix_io_register
Example-b8-1\timing_sim\work\hcstratix_jtag
Example-b8-2\timing_sim\work\hcstratix_jtag
Example-b8-1\timing_sim\work\hcstratix_lcell
Example-b8-2\timing_sim\work\hcstratix_lcell
Example-b8-1\timing_sim\work\hcstratix_lcell_register
Example-b8-2\timing_sim\work\hcstratix_lcell_register
Example-b8-1\timing_sim\work\hcstratix_lvds_receiver
Example-b8-2\timing_sim\work\hcstratix_lvds_receiver
Example-b8-1\timing_sim\work\hcstratix_lvds_rx_parallel_register
Example-b8-2\timing_sim\work\hcstratix_lvds_rx_parallel_register
Example-b8-1\timing_sim\work\hcstratix_lvds_transmitter
Example-b8-2\timing_sim\work\hcstratix_lvds_transmitter
Example-b8-1\timing_sim\work\hcstratix_lvds_tx_out_block
Example-b8-2\timing_sim\work\hcstratix_lvds_tx_out_block
Example-b8-1\timing_sim\work\hcstratix_lvds_tx_parallel_register
Example-b8-2\timing_sim\work\hcstratix_lvds_tx_parallel_register
Example-b8-1\timing_sim\work\hcstratix_mac_mult
Example-b8-2\timing_sim\work\hcstratix_mac_mult
Example-b8-1\timing_sim\work\hcstratix_mac_mult_internal
Example-b8-2\timing_sim\work\hcstratix_mac_mult_internal
Example-b8-1\timing_sim\work\hcstratix_mac_out
Example-b8-2\timing_sim\work\hcstratix_mac_out
Example-b8-1\timing_sim\work\hcstratix_mac_out_internal
Example-b8-2\timing_sim\work\hcstratix_mac_out_internal
Example-b8-1\timing_sim\work\hcstratix_mac_register
Example-b8-2\timing_sim\work\hcstratix_mac_register
Example-b8-1\timing_sim\work\hcstratix_pll
Example-b8-2\timing_sim\work\hcstratix_pll
Example-b8-1\timing_sim\work\hcstratix_ram_block
Example-b8-2\timing_sim\work\hcstratix_ram_block
Example-b8-1\timing_sim\work\hcstratix_ram_clear
Example-b8-2\timing_sim\work\hcstratix_ram_clear
Example-b8-1\timing_sim\work\hcstratix_ram_internal
Example-b8-2\timing_sim\work\hcstratix_ram_internal
Example-b8-1\timing_sim\work\hcstratix_ram_register
Example-b8-2\timing_sim\work\hcstratix_ram_register
Example-b8-1\timing_sim\work\hcstratix_rublock
Example-b8-2\timing_sim\work\hcstratix_rublock
Example-b8-1\timing_sim\work\hssi_fifo
Example-b8-2\timing_sim\work\hssi_fifo
Example-b8-1\timing_sim\work\hssi_pll
Example-b8-2\timing_sim\work\hssi_pll
Example-b8-1\timing_sim\work\hssi_rx
Example-b8-2\timing_sim\work\hssi_rx
Example-b8-1\timing_sim\work\hssi_tx
Example-b8-2\timing_sim\work\hssi_tx
Example-b4-2\Solution\IP_ENC\hw
Example-b8-1\timing_sim\work\io_buf_opdrn
Example-b8-2\timing_sim\work\io_buf_opdrn
Example-b8-1\timing_sim\work\io_buf_tri
Example-b8-2\timing_sim\work\io_buf_tri
Example-b4-2\Project\IP_ENC
Example-b4-2\Solution\IP_ENC\iptb_ed8b10b_temp41893
Example-b4-2\Solution\IP_ENC
Example-b8-1\timing_sim\work\latch
Example-b8-2\timing_sim\work\latch
Example-b8-1\timing_sim\work\lcell
Example-b8-2\timing_sim\work\lcell
Example-b8-1\timing_sim\work\lpm_abs
Example-b8-2\timing_sim\work\lpm_abs
Example-b8-1\timing_sim\work\lpm_add_sub
Example-b8-2\timing_sim\work\lpm_add_sub
Example-b8-1\timing_sim\work\lpm_and
Example-b8-2\timing_sim\work\lpm_and
Example-b8-1\timing_sim\work\lpm_bipad
Example-b8-2\timing_sim\work\lpm_bipad
Example-b8-1\timing_sim\work\lpm_bustri
Example-b8-2\timing_sim\work\lpm_bustri
Example-b8-1\timing_sim\work\lpm_clshift
Example-b8-2\timing_sim\work\lpm_clshift
Example-b8-1\timing_sim\work\lpm_compare
Example-b8-2\timing_sim\work\lpm_compare
Example-b8-1\timing_sim\work\lpm_constant
Example-b8-2\timing_sim\work\lpm_constant
Example-b8-1\timing_sim\work\lpm_counter
Example-b8-2\timing_sim\work\lpm_counter
Example-b8-1\timing_sim\work\lpm_decode
Example-b8-2\timing_sim\work\lpm_decode
Example-b8-1\timing_sim\work\lpm_divide
Example-b8-2\timing_sim\work\lpm_divide
Example-b8-1\timing_sim\work\lpm_ff
Example-b8-2\timing_sim\work\lpm_ff
Example-b8-1\timing_sim\work\lpm_fifo
Example-b8-2\timing_sim\work\lpm_fifo
Example-b8-1\timing_sim\work\lpm_fifo_dc
Example-b8-1\timing_sim\work\lpm_fifo_dc_async
Example-b8-1\timing_sim\work\lpm_fifo_dc_dffpipe
Example-b8-1\timing_sim\work\lpm_fifo_dc_fefifo
Example-b8-1\timing_sim\work\lpm_inpad
Example-b8-1\timing_sim\work\lpm_inv
Example-b8-1\timing_sim\work\lpm_latch
Example-b8-1\timing_sim\work\lpm_mult
Example-b8-1\timing_sim\work\lpm_mux
Example-b8-1\timing_sim\work\lpm_or
Example-b8-1\timing_sim\work\lpm_outpad
Example-b8-1\timing_sim\work\lpm_ram_dp
Example-b8-1\timing_sim\work\lpm_ram_dq
Example-b8-1\timing_sim\work\lpm_ram_io
Example-b8-1\timing_sim\work\lpm_rom
Example-b8-1\timing_sim\work\lpm_shiftreg
Example-b8-1\timing_sim\work\lpm_xor
Example-b8-1\timing_sim\work\m_cntr
Example-b8-6\source\mixed
Example-b8-6\Synplify_Pro\source\mixed
Example-b8-1\pll_ram\simulation\modelsim
Example-b8-1\source\post-simulation\modelsim
Example-b8-2\pll_ram\simulation\modelsim
Example-b8-2\source\post-simulation\modelsim
Example-b8-1\timing_sim\work\mux21
Example-b8-1\timing_sim\work\mux41
Example-b8-1\timing_sim\work\n_cntr
Example-b8-1\timing_sim\work\nmux21
Example-b8-1\timing_sim\work\oper_add
Example-b8-1\timing_sim\work\oper_addsub
Example-b8-1\timing_sim\work\oper_bus_mux
Example-b8-1\timing_sim\work\oper_decoder
Example-b8-1\timing_sim\work\oper_div
Example-b8-1\timing_sim\work\oper_left_shift
Example-b8-1\timing_sim\work\oper_less_than
Example-b8-1\timing_sim\work\oper_mod
Example-b8-1\timing_sim\work\oper_mult
Example-b8-1\timing_sim\work\oper_mux
Example-b8-1\timing_sim\work\oper_right_shift
Example-b8-1\timing_sim\work\oper_rotate_left
Example-b8-1\timing_sim\work\oper_rotate_right
Example-b8-1\timing_sim\work\oper_selector
Example-b8-1\timing_sim\work\parallel_add
Example-b8-1\func_sim\work\pll_ram
Example-b8-1\timing_sim\work\pll_ram
Example-b8-2\func_sim\work\pll_ram
Example-b8-1\pll_ram\db\pll_ram_hier_info
Example-b8-2\pll_ram\db\pll_ram_hier_info
Example-b8-1\pll_ram\db\pll_ram_syn_hier_info
Example-b8-2\pll_ram\db\pll_ram_syn_hier_info
Example-b8-1\timing_sim\work\pll_ram_tb
Example-b8-2\func_sim\work\pll_ram_tb
Example-b8-1\timing_sim\work\pll_reg
Example-b8-1\func_sim\work\pllx2
Example-b8-2\func_sim\work\pllx2
Example-b8-1\source\post-simulation
Example-b8-2\source\post-simulation
Example-b4-1\Project
Example-b4-2\Project
Example-b8-6\Synplify_Pro\rev_1
Example-b8-6\Synplify_Pro\rev_2
Example-b8-6\Synplify_Pro\rev_3
Example-b8-1\timing_sim\work\scale_cntr
Example-b8-1\timing_sim\work\scfifo
Example-b4-2\Solution\IP_ENC\iptb_ed8b10b_temp41893\simgen
Example-b4-1\Project\Simulation
Example-b4-1\Solution\Simulation
Example-b4-2\Project\Simulation
Example-b4-2\Solution\Simulation
Example-b8-1\pll_ram\simulation
Example-b8-2\pll_ram\simulation
Example-b4-1\Solution
Example-b4-2\Solution
Example-b8-1\source
Example-b8-2\source
Example-b8-5\Source
Example-b8-6\source
Example-b8-6\Synplify_Pro\source
Example-b8-1\timing_sim\work\stratix_asynch_io
Example-b8-1\timing_sim\work\stratix_asynch_lcell
Example-b8-1\timing_sim\work\stratix_dll
Example-b8-1\timing_sim\work\stratix_io
Example-b8-1\timing_sim\work\stratix_io_register
Example-b8-1\timing_sim\work\stratix_jtag
Example-b8-1\timing_sim\work\stratix_lcell
Example-b8-1\timing_sim\work\stratix_lcell_register
Example-b8-1\timing_sim\work\stratix_lvds_receiver
Example-b8-1\timing_sim\work\stratix_lvds_rx
Example-b8-1\timing_sim\work\stratix_lvds_rx_parallel_register
Example-b8-1\timing_sim\work\stratix_lvds_transmitter
Example-b8-1\timing_sim\work\stratix_lvds_tx_out_block
Example-b8-1\timing_sim\work\stratix_lvds_tx_parallel_register
Example-b8-1\timing_sim\work\stratix_mac_mult
Example-b8-1\timing_sim\work\stratix_mac_mult_internal
Example-b8-1\timing_sim\work\stratix_mac_out
Example-b8-1\timing_sim\work\stratix_mac_out_internal
Example-b8-1\timing_sim\work\stratix_mac_register
Example-b8-1\timing_sim\work\stratix_pll
Example-b8-1\timing_sim\work\stratix_ram_block
Example-b8-1\timing_sim\work\stratix_ram_clear
Example-b8-1\timing_sim\work\stratix_ram_internal
Example-b8-1\timing_sim\work\stratix_ram_register
Example-b8-1\timing_sim\work\stratix_rublock
Example-b8-1\timing_sim\work\stratixgx_dpa_lvds_rx
Example-b8-1\timing_sim\work\stratixii_lvds_rx
Example-b8-1\timing_sim\work\stratixii_tx_outclk
Example-b8-1\timing_sim\work\stx_m_cntr
Example-b8-1\timing_sim\work\stx_n_cntr
Example-b8-1\timing_sim\work\stx_scale_cntr
Example-b8-6\Synplify_Pro\rev_1\syntmp
Example-b8-6\Synplify_Pro\rev_2\syntmp
Example-b8-6\Synplify_Pro\rev_3\syntmp
Example-b8-6\Synplify_Pro
Example-b8-5\demo_project\work\test_counter
Example-b8-2\timing_sim
Example-b8-1\func_sim\transcript
Example-b8-2\func_sim\transcript
Example-b8-1\timing_sim\transcript
Example-b8-1\timing_sim\work\tri_bus
Example-b8-6\source\mixed\verilog
Example-b8-6\source\verilog
Example-b8-6\Synplify_Pro\source\mixed\verilog
Example-b8-6\Synplify_Pro\source\verilog
Example-b8-6\source\mixed\vhdl
Example-b8-6\source\VHDL
Example-b8-6\Synplify_Pro\source\mixed\vhdl
Example-b8-6\Synplify_Pro\source\VHDL
Example-b8-2\func_sim\work
Example-b8-2\timing_sim\work
Example-b8-3\work
Example-b8-5\demo_project\work
Example-b4-1\Solution\TOP.bdf
Example-b4-2\Solution\TOPIP.bdf
Example-b4-1\Solution\DualPortRAM.bsf
Example-b4-2\Solution\ENC.bsf
Example-b4-2\Solution\IP_ENC\ENC.bsf
Example-b8-1\pll_ram\db\pll_ram(0).cnf.cdb
Example-b8-2\pll_ram\db\pll_ram(0).cnf.cdb
Example-b8-1\pll_ram\db\pll_ram(1).cnf.cdb
Example-b8-2\pll_ram\db\pll_ram(1).cnf.cdb
Example-b8-1\pll_ram\db\pll_ram(2).cnf.cdb
Example-b8-2\pll_ram\db\pll_ram(2).cnf.cdb
Example-b8-1\pll_ram\db\pll_ram(3).cnf.cdb
Example-b8-2\pll_ram\db\pll_ram(3).cnf.cdb
Example-b8-1\pll_ram\db\pll_ram(4).cnf.cdb
Example-b8-2\pll_ram\db\pll_ram(4).cnf.cdb
Example-b8-1\pll_ram\db\pll_ram(5).cnf.cdb
Example-b8-2\pll_ram\db\pll_ram(5).cnf.cdb
Example-b8-1\pll_ram\db\pll_ram(6).cnf.cdb
Example-b8-2\pll_ram\db\pll_ram(6).cnf.cdb
Example-b8-1\pll_ram\db\pll_ram(7).cnf.cdb
Example-b8-2\pll_ram\db\pll_ram(7).cnf.cdb
Example-b8-1\pll_ram\db\pll_ram.cmp.cdb
Example-b8-2\pll_ram\db\pll_ram.cmp.cdb
Example-b8-1\pll_ram\db\pll_ram.map.cdb
Example-b8-2\pll_ram\db\pll_ram.map.cdb
Example-b8-1\pll_ram\db\pll_ram.rtlv_sg.cdb
Example-b8-2\pll_ram\db\pll_ram.rtlv_sg.cdb
Example-b8-1\pll_ram\db\pll_ram.rtlv_sg_swap.cdb
Example-b8-2\pll_ram\db\pll_ram.rtlv_sg_swap.cdb
Example-b8-1\pll_ram\db\pll_ram.sgdiff.cdb
Example-b8-2\pll_ram\db\pll_ram.sgdiff.cdb
Example-b8-1\pll_ram\db\pll_ram.signalprobe.cdb
Example-b8-2\pll_ram\db\pll_ram.signalprobe.cdb
Example-b4-2\Solution\IP_ENC\ENC.cmp
Example-b8-1\timing_sim\work\carry\_primary.dat
Example-b8-1\timing_sim\work\exp\_primary.dat
Example-b8-1\timing_sim\work\lcell\_primary.dat
Example-b8-2\timing_sim\work\carry\_primary.dat
Example-b8-2\timing_sim\work\exp\_primary.dat
Example-b8-2\timing_sim\work\lcell\_primary.dat
Example-b8-1\timing_sim\work\global\_primary.dat
Example-b8-2\timing_sim\work\global\_primary.dat
Example-b8-1\timing_sim\work\cascade\_primary.dat
Example-b8-2\timing_sim\work\cascade\_primary.dat
Example-b8-1\timing_sim\work\and1\_primary.dat
Example-b8-2\timing_sim\work\and1\_primary.dat
Example-b8-1\timing_sim\work\nmux21\_primary.dat
Example-b8-1\timing_sim\work\carry_sum\_primary.dat
Example-b8-2\timing_sim\work\carry_sum\_primary.dat
Example-b8-1\timing_sim\work\bmux21\_primary.dat
Example-b8-2\timing_sim\work\bmux21\_primary.dat
Example-b8-1\timing_sim\work\b5mux21\_primary.dat
Example-b8-2\timing_sim\work\b5mux21\_primary.dat
Example-b8-1\timing_sim\work\b17mux21\_primary.dat
Example-b8-2\timing_sim\work\b17mux21\_primary.dat
Example-b8-3\work\counter\_primary.dat
Example-b8-1\timing_sim\work\stratix_crcblock\_primary.dat
Example-b8-1\timing_sim\work\stratix_crcblock
Example-b8-1\timing_sim\work\hcstratix_crcblock\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_crcblock\_primary.dat
Example-b8-1\timing_sim\work\io_buf_opdrn\_primary.dat
Example-b8-1\timing_sim\work\io_buf_tri\_primary.dat
Example-b8-1\timing_sim\work
Example-b8-1\timing_sim
Example-b8-2\timing_sim\work\io_buf_opdrn\_primary.dat
Example-b8-2\timing_sim\work\io_buf_tri\_primary.dat
Example-b8-5\demo_project\work\test_counter\_primary.dat
Example-b8-1\timing_sim\work\dffp\_primary.dat
Example-b8-2\timing_sim\work\dffp\_primary.dat
Example-b8-1\timing_sim\work\mux21\_primary.dat
Example-b8-1\timing_sim\work\lpm_constant\_primary.dat
Example-b8-2\timing_sim\work\lpm_constant\_primary.dat
Example-b8-1\timing_sim\work\pll_reg\_primary.dat
Example-b8-1\timing_sim\work\@m@f_pll_reg\_primary.dat
Example-b8-2\timing_sim\work\@m@f_pll_reg\_primary.dat
Example-b8-1\timing_sim\work\stratix_jtag\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_jtag\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_jtag\_primary.dat
Example-b8-1\timing_sim\work\lpm_inv\_primary.dat
Example-b8-1\timing_sim\work\lpm_outpad\_primary.dat
Example-b8-1\timing_sim\work\lpm_inpad\_primary.dat
Example-b8-1\timing_sim\work\oper_mux\_primary.dat
Example-b8-1\timing_sim\work\oper_decoder\_primary.dat
Example-b8-1\timing_sim\work\stratix_ram_clear\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_ram_clear\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_ram_clear\_primary.dat
Example-b8-5\demo_project\work\counter\_primary.dat
Example-b8-1\timing_sim\work\arm_n_cntr\_primary.dat
Example-b8-2\timing_sim\work\arm_n_cntr\_primary.dat
Example-b8-1\timing_sim\work\oper_selector\_primary.dat
Example-b8-1\timing_sim\work\lpm_abs\_primary.dat
Example-b8-2\timing_sim\work\lpm_abs\_primary.dat
Example-b8-1\timing_sim\work\tri_bus\_primary.dat
Example-b8-1\timing_sim\work\mux41\_primary.dat
Example-b8-1\timing_sim\work\lpm_bipad\_primary.dat
Example-b8-2\timing_sim\work\lpm_bipad\_primary.dat
Example-b8-1\timing_sim\work\n_cntr\_primary.dat
Example-b8-1\timing_sim\work\and16\_primary.dat
Example-b8-2\timing_sim\work\and16\_primary.dat
Example-b8-1\timing_sim\work\m_cntr\_primary.dat
Example-b8-1\timing_sim\work\stx_n_cntr\_primary.dat
Example-b8-1\timing_sim\work\a_graycounter\_primary.dat
Example-b8-2\timing_sim\work\a_graycounter\_primary.dat
Example-b8-1\timing_sim\work\arm_m_cntr\_primary.dat
Example-b8-2\timing_sim\work\arm_m_cntr\_primary.dat
Example-b8-1\timing_sim\work\latch\_primary.dat
Example-b8-2\timing_sim\work\latch\_primary.dat
Example-b8-1\timing_sim\work\lpm_and\_primary.dat
Example-b8-2\timing_sim\work\lpm_and\_primary.dat
Example-b8-1\timing_sim\work\lpm_or\_primary.dat
Example-b8-1\timing_sim\work\lpm_xor\_primary.dat
Example-b8-1\timing_sim\work\stx_m_cntr\_primary.dat
Example-b8-1\func_sim\work\pll_ram\_primary.dat
Example-b8-2\func_sim\work\pll_ram\_primary.dat
Example-b8-1\timing_sim\work\dffe\_primary.dat
Example-b8-2\timing_sim\work\dffe\_primary.dat
Example-b8-1\timing_sim\work\dcfifo_dffpipe\_primary.dat
Example-b8-2\timing_sim\work\dcfifo_dffpipe\_primary.dat
Example-b8-1\timing_sim\work\lpm_fifo_dc_dffpipe\_primary.dat
Example-b8-1\timing_sim\work\lpm_bustri\_primary.dat
Example-b8-2\timing_sim\work\lpm_bustri\_primary.dat
Example-b8-1\timing_sim\work\oper_bus_mux\_primary.dat
Example-b8-1\func_sim\work\pll_ram_tb\_primary.dat
Example-b8-1\func_sim\work\pll_ram_tb
Example-b8-1\func_sim\work
Example-b8-1\func_sim
Example-b8-1\timing_sim\work\pll_ram_tb\_primary.dat
Example-b8-2\func_sim\work\pll_ram_tb\_primary.dat
Example-b8-1\timing_sim\work\oper_rotate_left\_primary.dat
Example-b8-1\timing_sim\work\oper_rotate_right\_primary.dat
Example-b8-1\timing_sim\work\oper_mult\_primary.dat
Example-b8-1\timing_sim\work\stratixii_tx_outclk\_primary.dat
Example-b8-1\timing_sim\work\oper_less_than\_primary.dat
Example-b8-1\timing_sim\work\oper_add\_primary.dat
Example-b8-1\timing_sim\work\oper_left_shift\_primary.dat
Example-b8-1\timing_sim\work\@p@r@i@m_@d@f@f@e\_primary.dat
Example-b8-2\timing_sim\work\@p@r@i@m_@d@f@f@e\_primary.dat
Example-b8-1\timing_sim\work\stratix_lvds_tx_out_block\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_lvds_tx_out_block\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_lvds_tx_out_block\_primary.dat
Example-b8-1\timing_sim\work\altshift_taps\_primary.dat
Example-b8-2\timing_sim\work\altshift_taps\_primary.dat
Example-b8-1\timing_sim\work\lpm_latch\_primary.dat
Example-b8-1\timing_sim\work\oper_right_shift\_primary.dat
Example-b8-1\timing_sim\work\oper_div\_primary.dat
Example-b8-1\timing_sim\work\oper_mod\_primary.dat
Example-b8-1\timing_sim\work\arm_scale_cntr\_primary.dat
Example-b8-2\timing_sim\work\arm_scale_cntr\_primary.dat
Example-b8-1\timing_sim\work\oper_addsub\_primary.dat
Example-b8-1\timing_sim\work\altddio_bidir\_primary.dat
Example-b8-2\timing_sim\work\altddio_bidir\_primary.dat
Example-b8-1\timing_sim\work\lpm_decode\_primary.dat
Example-b8-2\timing_sim\work\lpm_decode\_primary.dat
Example-b8-1\timing_sim\work\scale_cntr\_primary.dat
Example-b8-1\timing_sim\work\stx_scale_cntr\_primary.dat
Example-b8-1\timing_sim\work\hssi_tx\_primary.dat
Example-b8-2\timing_sim\work\hssi_tx\_primary.dat
Example-b8-1\func_sim\work\dpram8x32\_primary.dat
Example-b8-2\func_sim\work\dpram8x32\_primary.dat
Example-b8-1\timing_sim\work\lpm_mux\_primary.dat
Example-b8-1\timing_sim\work\stratix_lcell\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_lcell\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_lcell\_primary.dat
Example-b8-1\timing_sim\work\@l@p@m_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n\_primary.dat
Example-b8-2\timing_sim\work\@l@p@m_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n\_primary.dat
Example-b8-1\timing_sim\work\stratix_lvds_rx\_primary.dat
Example-b8-1\timing_sim\work\lpm_fifo_dc\_primary.dat
Example-b8-1\func_sim\work\pllx2\_primary.dat
Example-b8-2\func_sim\work\pllx2\_primary.dat
Example-b8-1\timing_sim\work\stratix_io_register\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_io_register\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_io_register\_primary.dat
Example-b8-1\timing_sim\work\dcfifo_fefifo\_primary.dat
Example-b8-2\timing_sim\work\dcfifo_fefifo\_primary.dat
Example-b8-1\timing_sim\work\@m@f_ram7x20_syn\_primary.dat
Example-b8-2\timing_sim\work\@m@f_ram7x20_syn\_primary.dat
Example-b8-1\timing_sim\work\lpm_ff\_primary.dat
Example-b8-2\timing_sim\work\lpm_ff\_primary.dat
Example-b8-1\timing_sim\work\lpm_compare\_primary.dat
Example-b8-2\timing_sim\work\lpm_compare\_primary.dat
Example-b8-1\timing_sim\work\lpm_shiftreg\_primary.dat
Example-b8-1\timing_sim\work\altddio_in\_primary.dat
Example-b8-2\timing_sim\work\altddio_in\_primary.dat
Example-b8-1\timing_sim\work\dcfifo\_primary.dat
Example-b8-2\timing_sim\work\dcfifo\_primary.dat
Example-b8-1\timing_sim\work\stratix_lvds_rx_parallel_register\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_lvds_rx_parallel_register\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_lvds_rx_parallel_register\_primary.dat
Example-b8-1\timing_sim\work\stratix_lvds_receiver\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_lvds_receiver\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_lvds_receiver\_primary.dat
Example-b8-1\timing_sim\work\lpm_fifo_dc_fefifo\_primary.dat
Example-b8-1\timing_sim\work\stratix_lvds_transmitter\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_lvds_transmitter\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_lvds_transmitter\_primary.dat
Example-b8-1\timing_sim\work\altsqrt\_primary.dat
Example-b8-2\timing_sim\work\altsqrt\_primary.dat
Example-b8-1\timing_sim\work\hssi_rx\_primary.dat
Example-b8-2\timing_sim\work\hssi_rx\_primary.dat
Example-b8-1\timing_sim\work\lpm_mult\_primary.dat
Example-b8-1\timing_sim\work\parallel_add\_primary.dat
Example-b8-1\timing_sim\work\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\_primary.dat
Example-b8-2\timing_sim\work\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\_primary.dat
Example-b8-1\timing_sim\work\stratix_lcell_register\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_lcell_register\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_lcell_register\_primary.dat
Example-b8-1\timing_sim\work\altddio_out\_primary.dat
Example-b8-2\timing_sim\work\altddio_out\_primary.dat
Example-b8-1\timing_sim\work\stratix_lvds_tx_parallel_register\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_lvds_tx_parallel_register\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_lvds_tx_parallel_register\_primary.dat
Example-b8-1\timing_sim\work\lpm_add_sub\_primary.dat
Example-b8-2\timing_sim\work\lpm_add_sub\_primary.dat
Example-b8-1\timing_sim\work\lpm_rom\_primary.dat
Example-b8-1\timing_sim\work\hssi_fifo\_primary.dat
Example-b8-2\timing_sim\work\hssi_fifo\_primary.dat
Example-b8-1\timing_sim\work\lpm_clshift\_primary.dat
Example-b8-2\timing_sim\work\lpm_clshift\_primary.dat
Example-b8-1\timing_sim\work\lpm_counter\_primary.dat
Example-b8-2\timing_sim\work\lpm_counter\_primary.dat
Example-b8-1\timing_sim\work\stratix_asynch_io\_primary.dat
Example-b8-1\timing_sim\work\@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\_primary.dat
Example-b8-2\timing_sim\work\@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_asynch_io\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_asynch_io\_primary.dat
Example-b8-1\timing_sim\work\lpm_divide\_primary.dat
Example-b8-2\timing_sim\work\lpm_divide\_primary.dat
Example-b8-1\timing_sim\work\lpm_ram_io\_primary.dat
Example-b8-1\timing_sim\work\alt_exc_dpram\_primary.dat
Example-b8-2\timing_sim\work\alt_exc_dpram\_primary.dat
Example-b8-1\timing_sim\work\lpm_ram_dq\_primary.dat
Example-b8-1\timing_sim\work\stratix_rublock\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_rublock\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_rublock\_primary.dat
Example-b8-1\timing_sim\work\altaccumulate\_primary.dat
Example-b8-2\timing_sim\work\altaccumulate\_primary.dat
Example-b8-1\timing_sim\work\stratix_mac_mult\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_mac_mult\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_mac_mult\_primary.dat
Example-b8-1\timing_sim\work\stratix_io\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_io\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_io\_primary.dat
Example-b8-1\timing_sim\work\lpm_ram_dp\_primary.dat
Example-b8-1\timing_sim\work\stratix_dll\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_dll\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_dll\_primary.dat
Example-b8-1\timing_sim\work\dcfifo_sync\_primary.dat
Example-b8-2\timing_sim\work\dcfifo_sync\_primary.dat
Example-b8-1\timing_sim\work\altdpram\_primary.dat
Example-b8-2\timing_sim\work\altdpram\_primary.dat
Example-b8-1\timing_sim\work\lpm_fifo\_primary.dat
Example-b8-2\timing_sim\work\lpm_fifo\_primary.dat
Example-b8-1\timing_sim\work\scfifo\_primary.dat
Example-b8-1\timing_sim\work\dcfifo_async\_primary.dat
Example-b8-2\timing_sim\work\dcfifo_async\_primary.dat
Example-b8-1\timing_sim\work\stratixii_lvds_rx\_primary.dat
Example-b8-1\timing_sim\work\stratix_asynch_lcell\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_asynch_lcell\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_asynch_lcell\_primary.dat
Example-b8-1\timing_sim\work\hssi_pll\_primary.dat
Example-b8-2\timing_sim\work\hssi_pll\_primary.dat
Example-b8-1\timing_sim\work\lpm_fifo_dc_async\_primary.dat
Example-b8-1\timing_sim\work\stratix_mac_mult_internal\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_mac_mult_internal\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_mac_mult_internal\_primary.dat
Example-b8-1\timing_sim\work\stratix_mac_out\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_mac_out\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_mac_out\_primary.dat
Example-b8-1\timing_sim\work\stratixgx_dpa_lvds_rx\_primary.dat
Example-b8-1\timing_sim\work\stratix_mac_out_internal\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_mac_out_internal\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_mac_out_internal\_primary.dat
Example-b8-1\timing_sim\work\stratix_mac_register\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_mac_register\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_mac_register\_primary.dat
Example-b8-1\timing_sim\work\alt3pram\_primary.dat
Example-b8-2\timing_sim\work\alt3pram\_primary.dat
Example-b8-1\timing_sim\work\altfp_mult\_primary.dat
Example-b8-2\timing_sim\work\altfp_mult\_primary.dat
Example-b8-1\timing_sim\work\altcdr_tx\_primary.dat
Example-b8-2\timing_sim\work\altcdr_tx\_primary.dat
Example-b8-1\timing_sim\work\altlvds_tx\_primary.dat
Example-b8-2\timing_sim\work\altlvds_tx\_primary.dat
Example-b8-1\timing_sim\work\altclklock\_primary.dat
Example-b8-2\timing_sim\work\altclklock\_primary.dat
Example-b8-1\timing_sim\work\altcdr_rx\_primary.dat
Example-b8-2\timing_sim\work\altcdr_rx\_primary.dat
Example-b8-1\timing_sim\work\altlvds_rx\_primary.dat
Example-b8-2\timing_sim\work\altlvds_rx\_primary.dat
Example-b8-1\timing_sim\work\stratix_ram_block\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_ram_block\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_ram_block\_primary.dat
Example-b8-1\timing_sim\work\altqpram\_primary.dat
Example-b8-2\timing_sim\work\altqpram\_primary.dat
Example-b8-1\timing_sim\work\stratix_ram_register\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_ram_register\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_ram_register\_primary.dat
Example-b8-1\timing_sim\work\altsyncram\_primary.dat
Example-b8-2\timing_sim\work\altsyncram\_primary.dat
Example-b8-1\timing_sim\work\altpll\_primary.dat
Example-b8-2\timing_sim\work\altpll\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_ram_internal\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_ram_internal\_primary.dat
Example-b8-1\timing_sim\work\stratix_ram_internal\_primary.dat
Example-b8-1\timing_sim\work\alt_exc_upcore\_primary.dat
Example-b8-2\timing_sim\work\alt_exc_upcore\_primary.dat
Example-b8-1\timing_sim\work\altmult_accum\_primary.dat
Example-b8-2\timing_sim\work\altmult_accum\_primary.dat
Example-b8-1\timing_sim\work\pll_ram\_primary.dat
Example-b8-1\timing_sim\work\altmult_add\_primary.dat
Example-b8-2\timing_sim\work\altmult_add\_primary.dat
Example-b8-1\timing_sim\work\altcam\_primary.dat
Example-b8-2\timing_sim\work\altcam\_primary.dat
Example-b8-1\timing_sim\work\@m@f_stratixii_pll\_primary.dat
Example-b8-2\timing_sim\work\@m@f_stratixii_pll\_primary.dat
Example-b8-1\timing_sim\work\stratix_pll\_primary.dat
Example-b8-1\timing_sim\work\hcstratix_pll\_primary.dat
Example-b8-2\timing_sim\work\hcstratix_pll\_primary.dat
Example-b8-1\timing_sim\work\@m@f_stratix_pll\_primary.dat
Example-b8-2\timing_sim\work\@m@f_stratix_pll\_primary.dat
Example-b8-1\pll_ram\db\pll_ram.db_info
Example-b8-2\pll_ram\db\pll_ram.db_info
Example-b8-1\pll_ram\db\pll_ram.cmp.ddb
Example-b8-2\pll_ram\db\pll_ram.cmp.ddb
Example-b8-3\counter.do
Example-b8-4\gold_sim.do
Example-b8-4\sec_sim.do
Example-b4-2\Project\Simulation\sim.do
Example-b4-2\Solution\Simulation\sim.do
Example-b4-1\Project\Simulation\sim.do
Example-b4-1\Solution\Simulation\sim.do
Example-b8-3\stimulus.do
Example-b4-1\Project\Simulation\wave.do
Example-b4-1\Solution\Simulation\wave.do
Example-b4-2\Project\Simulation\wave.do
Example-b4-2\Solution\Simulation\wave.do
Example-b8-1\func_sim\wave.do
Example-b8-2\func_sim\wave.do
Example-b8-1\pll_ram\pll_ram.done
Example-b8-2\pll_ram\pll_ram.done
Example-b8-1\pll_ram\pll_ram.fit.eqn
Example-b8-2\pll_ram\pll_ram.fit.eqn
Example-b8-1\pll_ram\pll_ram.map.eqn
Example-b8-2\pll_ram\pll_ram.map.eqn
Example-b8-6\Synplify_Pro\rev_1\ALU.fse
Example-b8-6\Synplify_Pro\rev_1\HDL_DEMO.fse
Example-b8-6\Synplify_Pro\rev_2\top.fse
Example-b8-6\Synplify_Pro\rev_3\top1.fse
Example-b8-6\Synplify_Pro\rev_1\fsmviewer.fsm
Example-b8-1\pll_ram\db\pll_ram(0).cnf.hdb
Example-b8-2\pll_ram\db\pll_ram(0).cnf.hdb
Example-b8-1\pll_ram\db\pll_ram(1).cnf.hdb
Example-b8-2\pll_ram\db\pll_ram(1).cnf.hdb
Example-b8-1\pll_ram\db\pll_ram(2).cnf.hdb
Example-b8-2\pll_ram\db\pll_ram(2).cnf.hdb
Example-b8-1\pll_ram\db\pll_ram(3).cnf.hdb
Example-b8-2\pll_ram\db\pll_ram(3).cnf.hdb
Example-b8-1\pll_ram\db\pll_ram(4).cnf.hdb
Example-b8-2\pll_ram\db\pll_ram(4).cnf.hdb
Example-b8-1\pll_ram\db\pll_ram(5).cnf.hdb
Example-b8-2\pll_ram\db\pll_ram(5).cnf.hdb
Example-b8-1\pll_ram\db\pll_ram(6).cnf.hdb
Example-b8-2\pll_ram\db\pll_ram(6).cnf.hdb
Example-b8-1\pll_ram\db\pll_ram(7).cnf.hdb
Example-b8-2\pll_ram\db\pll_ram(7).cnf.hdb
Example-b8-1\pll_ram\db\pll_ram.cmp.hdb
Example-b8-2\pll_ram\db\pll_ram.cmp.hdb
Example-b8-1\pll_ram\db\pll_ram.map.hdb
Example-b8-2\pll_ram\db\pll_ram.map.hdb
Example-b8-1\pll_ram\db\pll_ram.pre_map.hdb
Example-b8-2\pll_ram\db\pll_ram.pre_map.hdb
Example-b8-1\pll_ram\db\pll_ram.project.hdb
Example-b8-2\pll_ram\db\pll_ram.project.hdb
Example-b8-1\pll_ram\db\pll_ram.rtlv.hdb
Example-b8-2\pll_ram\db\pll_ram.rtlv.hdb
Example-b8-1\pll_ram\db\pll_ram.sgdiff.hdb
Example-b8-2\pll_ram\db\pll_ram.sgdiff.hdb
Example-b8-1\pll_ram\db\pll_ram.hif
Example-b8-2\pll_ram\db\pll_ram.hif
Example-b8-1\pll_ram\db\pll_ram.icc
Example-b8-2\pll_ram\db\pll_ram.icc
Example-b4-2\Solution\IP_ENC\ENC.inc
Example-b8-1\func_sim\func_sim.mpf
Example-b8-2\func_sim\func_sim.mpf
Example-b8-1\timing_sim\timing_sim.mpf
Example-b8-1\func_sim\func_sim.cr.mti
Example-b8-2\func_sim\func_sim.cr.mti
Example-b8-1\timing_sim\timing_sim.cr.mti
Example-b4-2\Solution\IP_ENC\ENC_aot1151_enc8b10b.ocp
Example-b8-1\pll_ram\pll_ram.pin
Example-b8-2\pll_ram\pll_ram.pin
Example-b8-6\Synplify_Pro\rev_1\syntmp\ALU.plg
Example-b8-6\Synplify_Pro\rev_1\syntmp\HDL_DEMO.plg
Example-b8-6\Synplify_Pro\rev_3\syntmp\mux.plg
Example-b8-6\Synplify_Pro\rev_3\syntmp\rotate.plg
Example-b8-6\Synplify_Pro\rev_3\syntmp\top.plg
Example-b8-6\Synplify_Pro\rev_2\syntmp\top.plg
Example-b8-6\Synplify_Pro\rev_3\syntmp\top1.plg
Example-b8-1\pll_ram\pll_ram.pof
Example-b8-2\pll_ram\pll_ram.pof
Example-b8-6\Synplify_Pro\ALU_Syn_2.prd
Example-b8-6\Synplify_Pro\ALU_Syn_demo.prd
Example-b8-6\Synplify_Pro\Mix_src.prd
Example-b8-6\Synplify_Pro\Mix_src_vhdl.prd
Example-b8-6\Synplify_Pro\Mix_src_vlog.prd
Example-b8-6\Synplify_Pro\MyWorkspace.prd
Example-b8-6\Synplify_Pro\ALU_Syn_2.prj
Example-b8-6\Synplify_Pro\ALU_Syn_demo.prj
Example-b8-6\Synplify_Pro\Mix_src_vhdl.prj
Example-b8-6\Synplify_Pro\Mix_src_vlog.prj
Example-b8-6\Synplify_Pro\MyWorkspace.prj
Example-b8-1\pll_ram\db\pll_ram.asm.qmsg
Example-b8-2\pll_ram\db\pll_ram.asm.qmsg
Example-b8-1\pll_ram\db\pll_ram.csf.qmsg
Example-b8-2\pll_ram\db\pll_ram.csf.qmsg
Example-b8-1\pll_ram\db\pll_ram.eda.qmsg
Example-b8-2\pll_ram\db\pll_ram.eda.qmsg
Example-b8-1\pll_ram\db\pll_ram.fit.qmsg
Example-b8-2\pll_ram\db\pll_ram.fit.qmsg
Example-b8-1\pll_ram\db\pll_ram.map.qmsg
Example-b8-2\pll_ram\db\pll_ram.map.qmsg
Example-b8-1\pll_ram\db\pll_ram.tan.qmsg
Example-b8-2\pll_ram\db\pll_ram.tan.qmsg
Example-b8-1\pll_ram\pll_ram.qpf
Example-b8-2\pll_ram\pll_ram.qpf
Example-b4-1\Project\TOP.qpf
Example-b4-1\Solution\TOP.qpf
Example-b4-2\Solution\TOPIP.qpf
Example-b8-1\pll_ram\db\pll_ram_cmp.qrpt
Example-b8-2\pll_ram\db\pll_ram_cmp.qrpt
Example-b8-1\pll_ram\pll_ram.qsf
Example-b8-2\pll_ram\pll_ram.qsf
Example-b4-1\Project\TOP.qsf
Example-b4-1\Solution\TOP.qsf
Example-b4-2\Solution\TOPIP.qsf
Example-b8-1\pll_ram\pll_ram.qws
Example-b8-2\pll_ram\pll_ram.qws
Example-b8-1\pll_ram\db\pll_ram.cmp.rdb
Example-b8-1\pll_ram
Example-b8-1
Example-b8-2\pll_ram\db\pll_ram.cmp.rdb
Example-b8-6\Synplify_Pro\rev_2\.recordref
Example-b8-6\Synplify_Pro\rev_3\.recordref
Example-b8-1\pll_ram\pll_ram.asm.rpt
Example-b8-2\pll_ram\pll_ram.asm.rpt
Example-b8-1\pll_ram\pll_ram.eda.rpt
Example-b8-2\pll_ram\pll_ram.eda.rpt
Example-b8-1\pll_ram\pll_ram.fit.rpt
Example-b8-2\pll_ram\pll_ram.fit.rpt
Example-b8-1\pll_ram\pll_ram.flow.rpt
Example-b8-2\pll_ram\pll_ram.flow.rpt
Example-b8-1\pll_ram\pll_ram.map.rpt
Example-b8-2\pll_ram\pll_ram.map.rpt
Example-b8-1\pll_ram\pll_ram.tan.rpt
Example-b8-2\pll_ram\pll_ram.tan.rpt
Example-b8-1\pll_ram\db\pll_ram.pll_ram.sld_design_entry.sci
Example-b8-2\pll_ram\db\pll_ram.pll_ram.sld_design_entry.sci
Example-b8-6\Synplify_Pro\ALU_Syn_demo.sdc
Example-b8-6\Synplify_Pro\rev_1\AutoConstraint_alu.sdc
Example-b8-6\Synplify_Pro\rev_2\AutoConstraint_top.sdc
Example-b8-1\pll_ram\simulation\modelsim\pll_ram_v.sdo
Example-b8-1\source\post-simulation\modelsim\pll_ram_v.sdo
Example-b8-1\timing_sim\pll_ram_v.sdo
Example-b8-2\pll_ram\simulation\modelsim\pll_ram_v.sdo
Example-b8-2\source\post-simulation\modelsim\pll_ram_v.sdo
Example-b8-1\pll_ram\pll_ram.sof
Example-b8-2\pll_ram\pll_ram.sof
Example-b8-6\Synplify_Pro\rev_1\ALU.srd
Example-b8-6\Synplify_Pro\rev_1\HDL_DEMO.srd
Example-b8-6\Synplify_Pro\rev_2\top.srd
Example-b8-6\Synplify_Pro\rev_3\top1.srd
Example-b8-6\Synplify_Pro\rev_1\ALU.srm
Example-b8-6\Synplify_Pro\rev_1\HDL_DEMO.srm
Example-b8-6\Synplify_Pro\rev_1\HDL_DEMO_ta.srm
Example-b8-6\Synplify_Pro\rev_2\top.srm
Example-b8-6\Synplify_Pro\rev_3\top1.srm
Example-b8-6\Synplify_Pro\rev_1\ALU.srr
Example-b8-6\Synplify_Pro\rev_1\HDL_DEMO.srr
Example-b8-6\Synplify_Pro\rev_2\top.srr
Example-b8-6\Synplify_Pro\rev_3\top1.srr
Example-b8-6\Synplify_Pro\rev_1\ALU.srs
Example-b8-6\Synplify_Pro\rev_1\HDL_DEMO.srs
Example-b8-6\Synplify_Pro\rev_2\top.srs
Example-b8-6\Synplify_Pro\rev_3\top1.srs
Example-b8-1\pll_ram\pll_ram.tan.summary
Example-b8-2\pll_ram\pll_ram.tan.summary
Example-b8-6\Synplify_Pro\rev_1\ALU.sxr
Example-b8-6\Synplify_Pro\rev_1\HDL_DEMO.sxr
Example-b8-6\Synplify_Pro\rev_2\top.sxr
Example-b8-6\Synplify_Pro\rev_3\top1.sxr
Example-b8-6\Synplify_Pro\rev_1\HDL_DEMO.ta
Example-b8-6\Synplify_Pro\rev_1\HDL_DEMO.taq
Example-b8-6\Synplify_Pro\rev_1\ALU.tcl
Example-b8-6\Synplify_Pro\rev_1\ALU_cons.tcl
Example-b8-6\Synplify_Pro\rev_1\ALU_rm.tcl
Example-b4-2\Solution\IP_ENC\ENC_aot1151_enc8b10b.tcl
Example-b8-6\Synplify_Pro\rev_1\HDL_DEMO.tcl
Example-b8-6\Synplify_Pro\rev_1\HDL_DEMO_cons.tcl
Example-b8-6\Synplify_Pro\rev_1\HDL_DEMO_rm.tcl
Example-b8-6\Synplify_Pro\rev_2\top.tcl
Example-b8-6\Synplify_Pro\rev_2\top_cons.tcl
Example-b8-6\Synplify_Pro\rev_2\top_rm.tcl
Example-b8-6\Synplify_Pro\rev_3\top1.tcl
Example-b8-6\Synplify_Pro\rev_3\top1_cons.tcl
Example-b8-6\Synplify_Pro\rev_3\top1_rm.tcl
Example-b8-1\pll_ram\db\pll_ram.cmp.tdb
Example-b8-2\pll_ram\db\pll_ram.cmp.tdb
Example-b8-2\pll_ram\db\altsyncram_7bc1.tdf
Example-b8-2\pll_ram
Example-b8-2
Example-b8-1\pll_ram\db\altsyncram_7bc1.tdf
Example-b8-6\Synplify_Pro\rev_1\ALU.tlg
Example-b8-6\Synplify_Pro\rev_1\HDL_DEMO.tlg
Example-b8-6\Synplify_Pro\rev_2\layer0.tlg
Example-b8-6\Synplify_Pro\rev_3\layer0.tlg
Example-b8-6\Synplify_Pro\rev_3\layer1.tlg
Example-b8-6\Synplify_Pro\rev_2\layer1.tlg
Example-b8-6\Synplify_Pro\rev_2\layer2.tlg
Example-b8-6\Synplify_Pro\rev_3\layer2.tlg
Example-b8-1\Altera_lib_files\220model.v
Example-b8-2\Altera_lib_files\220model.v
Example-b4-2\Project\Simulation\220model.v
Example-b4-2\Solution\Simulation\220model.v
Example-b8-1\Altera_lib_files\altera_mf.v
Example-b8-2\Altera_lib_files\altera_mf.v
Example-b4-1\Project\Simulation\altera_mf.v
Example-b4-1\Solution\Simulation\altera_mf.v
Example-b4-2\Project\Simulation\altera_mf.v
Example-b4-2\Solution\Simulation\altera_mf.v
Example-b8-6\source\verilog\ALU.V
Example-b8-6\Synplify_Pro\source\verilog\ALU.V
Example-b8-4\beh_sram.v
Example-b8-3\counter.v
Example-b8-5\demo_project\counter.v
Example-b8-5\Source\counter.v
Example-b8-1\func_sim\dpram8x32.v
Example-b8-1\pll_ram\dpram8x32.v
Example-b8-1\source\dpram8x32.v
Example-b8-2\func_sim\dpram8x32.v
Example-b8-2\pll_ram\dpram8x32.v
Example-b8-2\source\dpram8x32.v
Example-b8-1\source\dpram8x32_bb.v
Example-b8-2\source\dpram8x32_bb.v
Example-b4-1\Solution\DualPortRAM.v
Example-b4-1\Solution\Simulation\DualPortRAM.v
Example-b4-2\Solution\ENC.v
Example-b4-2\Solution\IP_ENC\ENC.v
Example-b4-2\Solution\ENC_aot1151_enc8b10b.v
Example-b4-2\Solution\IP_ENC\ENC_aot1151_enc8b10b.v
Example-b4-2\Solution\IP_ENC\ENC_bb.v
Example-b4-2\Solution\IP_ENC\ENC_inst.v
Example-b4-2\Solution\IP_ENC\ENC_tb.v
Example-b4-2\Solution\Simulation\ENC_tb.v
Example-b8-6\source\verilog\HDL_DEMO.V
Example-b8-6\Synplify_Pro\source\verilog\HDL_DEMO.V
Example-b8-6\source\mixed\vhdl\mux.v
Example-b8-6\Synplify_Pro\source\mixed\vhdl\mux.v
Example-b8-6\source\mixed\verilog\mux21.v
Example-b8-6\Synplify_Pro\source\mixed\verilog\mux21.v
Example-b8-1\func_sim\pll_ram.v
Example-b8-1\pll_ram\pll_ram.v
Example-b8-1\source\pll_ram.v
Example-b8-2\func_sim\pll_ram.v
Example-b8-2\pll_ram\pll_ram.v
Example-b8-2\source\pll_ram.v
Example-b8-1\func_sim\pll_ram_tb.v
Example-b8-1\source\pll_ram_tb.v
Example-b8-1\timing_sim\pll_ram_tb.v
Example-b8-2\func_sim\pll_ram_tb.v
Example-b8-2\source\pll_ram_tb.v
Example-b8-1\func_sim\pllx2.v
Example-b8-1\pll_ram\pllx2.v
Example-b8-1\source\pllx2.v
Example-b8-2\func_sim\pllx2.v
Example-b8-2\pll_ram\pllx2.v
Example-b8-2\source\pllx2.v
Example-b8-1\source\pllx2_bb.v
Example-b8-2\source\pllx2_bb.v
Example-b8-6\source\mixed\vhdl\reg8.v
Example-b8-6\Synplify_Pro\source\mixed\vhdl\reg8.v
Example-b8-6\source\mixed\vhdl\rotate.v
Example-b8-6\Synplify_Pro\source\mixed\vhdl\rotate.v
Example-b4-2\Project\Simulation\sgate.v
Example-b4-2\Solution\Simulation\sgate.v
Example-b8-4\sm.v
Example-b8-4\sm_seq.v
Example-b8-1\Altera_lib_files\stratix_atoms.v
Example-b8-2\Altera_lib_files\stratix_atoms.v
Example-b8-5