文件名称:oc8051
介绍说明－－下载内容均来自于网络，请自行研究使用
51的VERILOG代码！适用于Xilinx的FPGA-51 VERILOG code! In Xilinx FPGA
(系统自动生成,下载前可以参看下载内容)
下载文件列表
压缩包 : 228607oc8051.rar 列表 oc8051 oc8051\.nclaunch.dd oc8051\asm oc8051\asm\cast.c oc8051\asm\counter_test.asm oc8051\asm\CVS oc8051\asm\CVS\Entries oc8051\asm\CVS\Repository oc8051\asm\CVS\Root oc8051\asm\DIV16U.asm oc8051\asm\divmul.c oc8051\asm\fib.c oc8051\asm\gcd.c oc8051\asm\hex oc8051\asm\hex\cast.hex oc8051\asm\hex\counter_test.hex oc8051\asm\hex\CVS oc8051\asm\hex\CVS\Entries oc8051\asm\hex\CVS\Repository oc8051\asm\hex\CVS\Root oc8051\asm\hex\div16u.hex oc8051\asm\hex\divmul.hex oc8051\asm\hex\fib.hex oc8051\asm\hex\gcd.hex oc8051\asm\hex\int2bin.hex oc8051\asm\hex\interrupt_test.hex oc8051\asm\hex\lcall.hex oc8051\asm\hex\negcnt.hex oc8051\asm\hex\r_bank.hex oc8051\asm\hex\serial_test.hex oc8051\asm\hex\sort.hex oc8051\asm\hex\sqroot.hex oc8051\asm\hex\testall.hex oc8051\asm\hex\timer_test.hex oc8051\asm\hex\xram.hex oc8051\asm\hex\xram_m.ihx oc8051\asm\in oc8051\asm\in\cast.in oc8051\asm\in\counter_test.in oc8051\asm\in\CVS oc8051\asm\in\CVS\Entries oc8051\asm\in\CVS\Repository oc8051\asm\in\CVS\Root oc8051\asm\in\div16u.in oc8051\asm\in\divmul.in oc8051\asm\in\fib.in oc8051\asm\in\gcd.in oc8051\asm\in\int2bin.in oc8051\asm\in\interrupt_test.in oc8051\asm\in\lcall.in oc8051\asm\in\negcnt.in oc8051\asm\in\oc8051_xrom.in oc8051\asm\in\r_bank.in oc8051\asm\in\serial_test.in oc8051\asm\in\sort.in oc8051\asm\in\sqroot.in oc8051\asm\in\testall.in oc8051\asm\in\test_xram.in oc8051\asm\in\timer2_test.in oc8051\asm\in\timer_test.in oc8051\asm\in\xram.in oc8051\asm\in\xram_m.in oc8051\asm\in\xrom_test.in oc8051\asm\int2bin.c oc8051\asm\interrupt_test.asm oc8051\asm\lcall.asm oc8051\asm\negcnt.c oc8051\asm\r_bank.asm oc8051\asm\serial_test.asm oc8051\asm\sort.c oc8051\asm\sqroot.c oc8051\asm\test.asm oc8051\asm\testall.asm oc8051\asm\testall.c oc8051\asm\timer2_test.asm oc8051\asm\timer_test.asm oc8051\asm\v oc8051\asm\v\cast.v oc8051\asm\v\counter_test.v oc8051\asm\v\CVS oc8051\asm\v\CVS\Entries oc8051\asm\v\CVS\Repository oc8051\asm\v\CVS\Root oc8051\asm\v\div16u.v oc8051\asm\v\divmul.v oc8051\asm\v\fib.v oc8051\asm\v\gcd.v oc8051\asm\v\int2bin.v oc8051\asm\v\interrupt_test.v oc8051\asm\v\lcall.v oc8051\asm\v\negcnt.v oc8051\asm\v\r_bank.v oc8051\asm\v\serial_test.v oc8051\asm\v\sort.v oc8051\asm\v\sqroot.v oc8051\asm\v\testall.v oc8051\asm\v\timer_test.v oc8051\asm\v\xram.v oc8051\asm\v\xram_m.v oc8051\asm\vec oc8051\asm\vec\cast.vec oc8051\asm\vec\counter_test.vec oc8051\asm\vec\CVS oc8051\asm\vec\CVS\Entries oc8051\asm\vec\CVS\Repository oc8051\asm\vec\CVS\Root oc8051\asm\vec\div16u.vec oc8051\asm\vec\divmul.vec oc8051\asm\vec\fib.vec oc8051\asm\vec\gcd.vec oc8051\asm\vec\int2bin.vec oc8051\asm\vec\interrupt_test.vec oc8051\asm\vec\lcall.vec oc8051\asm\vec\negcnt.vec oc8051\asm\vec\r_bank.vec oc8051\asm\vec\serial_test.vec oc8051\asm\vec\sort.vec oc8051\asm\vec\sqroot.vec oc8051\asm\vec\testall.vec oc8051\asm\vec\test_xram.vec oc8051\asm\vec\timer2_test.vec oc8051\asm\vec\timer_test.vec oc8051\asm\vec\xram_m.vec oc8051\asm\vec\xrom_test.vec oc8051\asm\xram.c oc8051\asm\xram_m.c oc8051\asm\xrom_test.asm oc8051\bench oc8051\bench\CVS oc8051\bench\CVS\Entries oc8051\bench\CVS\Repository oc8051\bench\CVS\Root oc8051\bench\in oc8051\bench\in\7seg.in oc8051\bench\in\blinkP10.in oc8051\bench\in\BLINKY.in oc8051\bench\in\calculator.in oc8051\bench\in\cast.in oc8051\bench\in\cordic.in oc8051\bench\in\counter_test.in oc8051\bench\in\Crc.in oc8051\bench\in\cubicroots.in oc8051\bench\in\CVS oc8051\bench\in\CVS\Entries oc8051\bench\in\CVS\Repository oc8051\bench\in\CVS\Root oc8051\bench\in\div16u.in oc8051\bench\in\divmul.in oc8051\bench\in\fib.in oc8051\bench\in\gcd.in oc8051\bench\in\int2bin.in oc8051\bench\in\interrupt_test.in oc8051\bench\in\interrupt_test2.in oc8051\bench\in\lcall.in oc8051\bench\in\mx_test.in oc8051\bench\in\mx_test.in~ oc8051\bench\in\negcnt.in oc8051\bench\in\normalize.in oc8051\bench\in\oc8051_rom.in oc8051\bench\in\oc8051_xrom.in oc8051\bench\in\pca_test.in oc8051\bench\in\pwm.in oc8051\bench\in\r_bank.in oc8051\bench\in\serial_test.in oc8051\bench\in\Sieve.in oc8051\bench\in\sort.in oc8051\bench\in\sqroot.in oc8051\bench\in\sqroot_1.in oc8051\bench\in\src.in oc8051\bench\in\testall.in oc8051\bench\in\test_xram.in oc8051\bench\in\timer0.in oc8051\bench\in\timer2_test.in oc8051\bench\in\timer_test.in oc8051\bench\in\wdog1.in oc8051\bench\in\wdog2.in oc8051\bench\in\wdog3.in oc8051\bench\in\xram.in oc8051\bench\in\xram_m.in oc8051\bench\in\xrom_test.in oc8051\bench\vec oc8051\bench\vec\CVS oc8051\bench\vec\CVS\Entries oc8051\bench\vec\CVS\Repository oc8051\bench\vec\CVS\Root oc8051\bench\verilog oc8051\bench\verilog\CVS oc8051\bench\verilog\CVS\Entries oc8051\bench\verilog\CVS\Repository oc8051\bench\verilog\CVS\Root oc8051\bench\verilog\oc8051_fpga_tb.v oc8051\bench\verilog\oc8051_serial.v oc8051\bench\verilog\oc8051_tb.v oc8051\bench\verilog\oc8051_timescale.v oc8051\bench\verilog\oc8051_uart_test.v oc8051\bench\verilog\oc8051_xram.v oc8051\bench\verilog\oc8051_xrom.v oc8051\CVS oc8051\CVS\Entries oc8051\CVS\Repository oc8051\CVS\Root oc8051\doc oc8051\doc\CVS oc8051\doc\CVS\Entries oc8051\doc\CVS\Repository oc8051\doc\CVS\Root oc8051\doc\pdf oc8051\doc\pdf\CVS oc8051\doc\pdf\CVS\Entries oc8051\doc\pdf\CVS\Repository oc8051\doc\pdf\CVS\Root oc8051\doc\pdf\oc8051_spec.pdf oc8051\doc\src oc8051\doc\src\CVS oc8051\doc\src\CVS\Entries oc8051\doc\src\CVS\Repository oc8051\doc\src\CVS\Root oc8051\doc\src\oc8051_design.doc oc8051\rtl oc8051\rtl\CVS oc8051\rtl\CVS\Entries oc8051\rtl\CVS\Repository oc8051\rtl\CVS\Root oc8051\rtl\verilog oc8051\rtl\verilog\CVS oc8051\rtl\verilog\CVS\Entries oc8051\rtl\verilog\CVS\Repository oc8051\rtl\verilog\CVS\Root oc8051\rtl\verilog\oc8051_acc.v oc8051\rtl\verilog\oc8051_alu.v oc8051\rtl\verilog\oc8051_alu_src_sel.v oc8051\rtl\verilog\oc8051_alu_test.v oc8051\rtl\verilog\oc8051_b_register.v oc8051\rtl\verilog\oc8051_cache_ram.v oc8051\rtl\verilog\oc8051_comp.v oc8051\rtl\verilog\oc8051_cy_select.v oc8051\rtl\verilog\oc8051_decoder.v oc8051\rtl\verilog\oc8051_defines.v oc8051\rtl\verilog\oc8051_divide.v oc8051\rtl\verilog\oc8051_dptr.v oc8051\rtl\verilog\oc8051_icache.v oc8051\rtl\verilog\oc8051_indi_addr.v oc8051\rtl\verilog\oc8051_int.v oc8051\rtl\verilog\oc8051_memory_interface.v oc8051\rtl\verilog\oc8051_multiply.v oc8051\rtl\verilog\oc8051_ports.v oc8051\rtl\verilog\oc8051_psw.v oc8051\rtl\verilog\oc8051_ram_256x8_two_bist.v oc8051\rtl\verilog\oc8051_ram_64x32_dual_bist.v oc8051\rtl\verilog\oc8051_ram_top.v oc8051\rtl\verilog\oc8051_rom.v oc8051\rtl\verilog\oc8051_sfr.v oc8051\rtl\verilog\oc8051_sp.v oc8051\rtl\verilog\oc8051_tc.v oc8051\rtl\verilog\oc8051_tc2.v oc8051\rtl\verilog\oc8051_timescale.v oc8051\rtl\verilog\oc8051_top.v oc8051\rtl\verilog\oc8051_uart.v oc8051\rtl\verilog\oc8051_wb_iinterface.v oc8051\rtl\verilog\read.me oc8051\sim oc8051\sim\CVS oc8051\sim\CVS\Entries oc8051\sim\CVS\Repository oc8051\sim\CVS\Root oc8051\sim\rtl_sim oc8051\sim\rtl_sim\bin oc8051\sim\rtl_sim\bin\cds.lib oc8051\sim\rtl_sim\bin\CVS oc8051\sim\rtl_sim\bin\CVS\Entries oc8051\sim\rtl_sim\bin\CVS\Repository oc8051\sim\rtl_sim\bin\CVS\Root oc8051\sim\rtl_sim\bin\hdl.var oc8051\sim\rtl_sim\bin\INCA_libs oc8051\sim\rtl_sim\bin\INCA_libs\CVS oc8051\sim\rtl_sim\bin\INCA_libs\CVS\Entries oc8051\sim\rtl_sim\bin\INCA_libs\CVS\Repository oc8051\sim\rtl_sim\bin\INCA_libs\CVS\Root oc8051\sim\rtl_sim\bin\INCA_libs\worklib oc8051\sim\rtl_sim\bin\INCA_libs\worklib\CVS oc8051\sim\rtl_sim\bin\INCA_libs\worklib\CVS\Entries oc8051\sim\rtl_sim\bin\INCA_libs\worklib\CVS\Repository oc8051\sim\rtl_sim\bin\INCA_libs\worklib\CVS\Root oc8051\sim\rtl_sim\bin\INCA_libs\worklib\inca.linux.138.pak oc8051\sim\rtl_sim\CVS oc8051\sim\rtl_sim\CVS\Entries oc8051\sim\rtl_sim\CVS\Repository oc8051\sim\rtl_sim\CVS\Root oc8051\sim\rtl_sim\log oc8051\sim\rtl_sim\log\CVS oc8051\sim\rtl_sim\log\CVS\Entries oc8051\sim\rtl_sim\log\CVS\Repository oc8051\sim\rtl_sim\log\CVS\Root oc8051\sim\rtl_sim\log\ncelab.log oc8051\sim\rtl_sim\log\ncsim.log oc8051\sim\rtl_sim\log\ncvlog.log oc8051\sim\rtl_sim\oc8051_ea.in oc8051\sim\rtl_sim\oc8051_eai.in oc8051\sim\rtl_sim\oc8051_eax.in oc8051\sim\rtl_sim\out oc8051\sim\rtl_sim\out\cast.out oc8051\sim\rtl_sim\out\counter_test.out oc8051\sim\rtl_sim\out\CVS oc8051\sim\rtl_sim\out\CVS\Entries oc8051\sim\rtl_sim\out\CVS\Repository oc8051\sim\rtl_sim\out\CVS\Root oc8051\sim\rtl_sim\out\div16u.out oc8051\sim\rtl_sim\out\divmul.out oc8051\sim\rtl_sim\out\fib.out oc8051\sim\rtl_sim\out\gcd.out oc8051\sim\rtl_sim\out\int2bin.out oc8051\sim\rtl_sim\out\interrupt_test.out oc8051\sim\rtl_sim\out\lcall.out oc8051\sim\rtl_sim\out\ncelab.out oc8051\sim\rtl_sim\out\ncprep.out oc8051\sim\rtl_sim\out\ncvlog.out oc8051\sim\rtl_sim\out\negcnt.out oc8051\sim\rtl_sim\out\r_bank.out oc8051\sim\rtl_sim\out\serial_test.out oc8051\sim\rtl_sim\out\sort.out oc8051\sim\rtl_sim\out\sqroot.out oc8051\sim\rtl_sim\out\testall.out oc8051\sim\rtl_sim\out\timer.out oc8051\sim\rtl_sim\out\timer_test.out oc8051\sim\rtl_sim\out\waves.shm oc8051\sim\rtl_sim\out\waves.shm\CVS oc8051\sim\rtl_sim\out\waves.shm\CVS\Entries oc8051\sim\rtl_sim\out\waves.shm\CVS\Repository oc8051\sim\rtl_sim\out\waves.shm\CVS\Root oc8051\sim\rtl_sim\out\xram_m.out oc8051\sim\rtl_sim\out\xrom_m.out oc8051\sim\rtl_sim\run oc8051\sim\rtl_sim\run\CVS oc8051\sim\rtl_sim\run\CVS\Entries oc8051\sim\rtl_sim\run\CVS\Repository oc8051\sim\rtl_sim\run\CVS\Root oc8051\sim\rtl_sim\run\internal.do oc8051\sim\rtl_sim\run\make oc8051\sim\rtl_sim\run\make_fpga oc8051\sim\rtl_sim\run\make_verilog oc8051\sim\rtl_sim\run\oc8051_defines.v oc8051\sim\rtl_sim\run\oc8051_timescale.v oc8051\sim\rtl_sim\run\run oc8051\sim\rtl_sim\run\run_sim.scr oc8051\sim\rtl_sim\run\verilog.log oc8051\sim\rtl_sim\src oc8051\sim\rtl_sim\src\CVS oc8051\sim\rtl_sim\src\CVS\Entries oc8051\sim\rtl_sim\src\CVS\Repository oc8051\sim\rtl_sim\src\CVS\Root oc8051\sim\rtl_sim\src\verilog oc8051\sim\rtl_sim\src\verilog\CVS oc8051\sim\rtl_sim\src\verilog\CVS\Entries oc8051\sim\rtl_sim\src\verilog\CVS\Repository oc8051\sim\rtl_sim\src\verilog\CVS\Root oc8051\sw oc8051\sw\CVS oc8051\sw\CVS\Entries oc8051\sw\CVS\Repository oc8051\sw\CVS\Root oc8051\sw\oc8051_Rom_Maker.exe oc8051\sw\read.me oc8051\sw\source oc8051\sw\source\CVS oc8051\sw\source\CVS\Entries oc8051\sw\source\CVS\Repository oc8051\sw\source\CVS\Root oc8051\sw\source\p8051Rom.dof oc8051\sw\source\p8051Rom.dpr oc8051\sw\source\p8051Rom.res oc8051\sw\source\uMain.dcu oc8051\sw\source\uMain.dfm oc8051\sw\source\uMain.pas oc8051\syn oc8051\syn\CVS oc8051\syn\CVS\Entries oc8051\syn\CVS\Repository oc8051\syn\CVS\Root oc8051\syn\src oc8051\syn\src\CVS oc8051\syn\src\CVS\Entries oc8051\syn\src\CVS\Repository oc8051\syn\src\CVS\Root oc8051\syn\src\verilog oc8051\syn\src\verilog\CVS oc8051\syn\src\verilog\CVS\Entries oc8051\syn\src\verilog\CVS\Repository oc8051\syn\src\verilog\CVS\Root oc8051\syn\src\verilog\disp.v oc8051\syn\src\verilog\oc8051_cache_ram.v oc8051\syn\src\verilog\oc8051_fpga_top.v oc8051\syn\src\verilog\oc8051_ram.v oc8051\syn\src\verilog\oc8051_rom.v oc8051\syn\src\verilog\read.me oc8051\syn\synplify oc8051\syn\synplify\CVS oc8051\syn\synplify\CVS\Entries oc8051\syn\synplify\CVS\Repository oc8051\syn\synplify\CVS\Root oc8051\syn\synplify\oc8051.prd oc8051\syn\synplify\oc8051.prj oc8051\syn\synplify\rev_1 oc8051\syn\synplify\rev_1\CVS oc8051\syn\synplify\rev_1\CVS\Entries oc8051\syn\synplify\rev_1\CVS\Repository oc8051\syn\synplify\rev_1\CVS\Root oc8051\syn\synplify\rev_2 oc8051\syn\synplify\rev_2\CVS oc8051\syn\synplify\rev_2\CVS\Entries oc8051\syn\synplify\rev_2\CVS\Repository oc8051\syn\synplify\rev_2\CVS\Root oc8051\syn\synplify\rev_3 oc8051\syn\synplify\rev_3\CVS oc8051\syn\synplify\rev_3\CVS\Entries oc8051\syn\synplify\rev_3\CVS\Repository oc8051\syn\synplify\rev_3\CVS\Root