文件名称:CANbuscontroller
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This source file may be used and distributed without restriction provided that this copyright statement is not removed from the file and that any derivative work contains the original copyright notice and the associated disclaimer. -This source file may be used and distribute d without restriction provided that this copyr ight statement is not removed from the file and t hat any derivative work contains the original c opyright notice and the associated disclaimer .
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压缩包 : 71477227canbuscontroller.rar 列表 bench\verilog\can_testbench.v bench\verilog\can_testbench_defines.v bench\verilog\CVS\Entries bench\verilog\CVS\Repository bench\verilog\CVS\Root bench\verilog\CVS bench\verilog\timescale.v bench\verilog bench rtl\verilog\can_acf.v rtl\verilog\can_bsp.v rtl\verilog\can_btl.v rtl\verilog\can_crc.v rtl\verilog\can_defines.v rtl\verilog\can_fifo.v rtl\verilog\can_ibo.v rtl\verilog\can_register.v rtl\verilog\can_registers.v rtl\verilog\can_register_asyn.v rtl\verilog\can_register_asyn_syn.v rtl\verilog\can_register_syn.v rtl\verilog\can_top.v rtl\verilog\CVS\Entries rtl\verilog\CVS\Repository rtl\verilog\CVS\Root rtl\verilog\CVS rtl\verilog\README.txt rtl\verilog rtl