文件名称:FPGA-CPLD_DesignTool
介绍说明－－下载内容均来自于网络，请自行研究使用
FPGA-CPLD_DesignTool,事例程序陆续上传请需要的朋友下载-FPGA-CPLD_DesignTool, examples please upload procedures need to have a friend download
(系统自动生成,下载前可以参看下载内容)
下载文件列表
压缩包 : 27796728fpga-cpld_designtool.rar 列表 Example-2-2\StateCAD_Demo\SIMTUT_TB.HLF Example-2-2\StateCAD_Demo\SIMTUT_TB.REG Example-2-2\StateCAD_Demo\SIMTUT_TB.TMP Example-2-2\StateCAD_Demo\SIMTUT_TB.VHD Example-2-2\StateCAD_Demo\TUT.DIA Example-2-2\StateCAD_Demo\TUT.vhd Example-2-2\StateCAD_Demo\TUT_TB.HLF Example-2-2\StateCAD_Demo\TUT_TB.REG Example-2-2\StateCAD_Demo\TUT_TB.TMP Example-2-2\StateCAD_Demo\TUT_TB.VHD Example-2-2\StateCAD_Demo\_import.dmo Example-2-2\StateCAD_Demo Example-2-2\源文件\SIMTUT_TB.VHD Example-2-2\源文件\TUT.DIA Example-2-2\源文件\TUT.vhd Example-2-2\源文件\TUT_TB.VHD Example-2-2\源文件 Example-2-2\示例说明.doc Example-2-2 Example-2-3\ECS_Demo\Mod7Cnt\.untf Example-2-3\ECS_Demo\Mod7Cnt\and4or2.sch Example-2-3\ECS_Demo\Mod7Cnt\and4or2.sprj Example-2-3\ECS_Demo\Mod7Cnt\and4or2.stx Example-2-3\ECS_Demo\Mod7Cnt\and4or2.sym Example-2-3\ECS_Demo\Mod7Cnt\and4or2.vf Example-2-3\ECS_Demo\Mod7Cnt\and5or2.sch Example-2-3\ECS_Demo\Mod7Cnt\and5or2.sprj Example-2-3\ECS_Demo\Mod7Cnt\and5or2.stx Example-2-3\ECS_Demo\Mod7Cnt\and5or2.sym Example-2-3\ECS_Demo\Mod7Cnt\and5or2.vf Example-2-3\ECS_Demo\Mod7Cnt\andnor2.sch Example-2-3\ECS_Demo\Mod7Cnt\andnor2.sprj Example-2-3\ECS_Demo\Mod7Cnt\andnor2.stx Example-2-3\ECS_Demo\Mod7Cnt\andnor2.sym Example-2-3\ECS_Demo\Mod7Cnt\andnor2.vf Example-2-3\ECS_Demo\Mod7Cnt\AndNor2_P.sch Example-2-3\ECS_Demo\Mod7Cnt\andnor2_p.sprj Example-2-3\ECS_Demo\Mod7Cnt\andnor2_p.stx Example-2-3\ECS_Demo\Mod7Cnt\andnor2_p.sym Example-2-3\ECS_Demo\Mod7Cnt\andnor2_p.vf Example-2-3\ECS_Demo\Mod7Cnt\automake.log Example-2-3\ECS_Demo\Mod7Cnt\bitgen.ut Example-2-3\ECS_Demo\Mod7Cnt\fdq.sch Example-2-3\ECS_Demo\Mod7Cnt\fdq.sprj Example-2-3\ECS_Demo\Mod7Cnt\fdq.stx Example-2-3\ECS_Demo\Mod7Cnt\fdq.sym Example-2-3\ECS_Demo\Mod7Cnt\fdq.vf Example-2-3\ECS_Demo\Mod7Cnt\Mod7Cnt.dhp Example-2-3\ECS_Demo\Mod7Cnt\Mod7Cnt.npl Example-2-3\ECS_Demo\Mod7Cnt\Mod7Cnt.ptf Example-2-3\ECS_Demo\Mod7Cnt\Mod7Cnt_ise5_bak.zip Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.bgn Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.bit Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.bld Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.cmd_log Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.dly Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.drc Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.lso Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.mrp Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.nc1 Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.ncd Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.ngc Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.ngd Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.ngm Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.ngr Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.pad Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.pad_txt Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.par Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.pcf Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.placed_ncd_tracker Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.prj Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.routed_ncd_tracker Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.sch Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.sprj Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.stx Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.sym Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.syr Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.twr Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.twx Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.ut Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.vf Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt.xpi Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt_bak.sch Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt_last_par.ncd Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt_map.ncd Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt_map.ngm Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt_ngdbuild.nav Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt_pad.csv Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt_pad.txt Example-2-3\ECS_Demo\Mod7Cnt\mode7cnt_vhdl.prj Example-2-3\ECS_Demo\Mod7Cnt\xst\work\hdllib.ref Example-2-3\ECS_Demo\Mod7Cnt\xst\work\vlg5B\fdq.bin Example-2-3\ECS_Demo\Mod7Cnt\xst\work\vlg5B Example-2-3\ECS_Demo\Mod7Cnt\xst\work\vlg77\and5or2.bin Example-2-3\ECS_Demo\Mod7Cnt\xst\work\vlg77 Example-2-3\ECS_Demo\Mod7Cnt\xst\work\vlg79\mode7cnt.bin Example-2-3\ECS_Demo\Mod7Cnt\xst\work\vlg79 Example-2-3\ECS_Demo\Mod7Cnt\xst\work\vlg7A\and4or2.bin Example-2-3\ECS_Demo\Mod7Cnt\xst\work\vlg7A Example-2-3\ECS_Demo\Mod7Cnt\xst\work Example-2-3\ECS_Demo\Mod7Cnt\xst Example-2-3\ECS_Demo\Mod7Cnt\_ngo\netlist.lst Example-2-3\ECS_Demo\Mod7Cnt\_ngo Example-2-3\ECS_Demo\Mod7Cnt\__projnav\and4or2.xst Example-2-3\ECS_Demo\Mod7Cnt\__projnav\and4or2._sprj Example-2-3\ECS_Demo\Mod7Cnt\__projnav\and4or2_jhdparse_tcl.rsp Example-2-3\ECS_Demo\Mod7Cnt\__projnav\and5or2.xst Example-2-3\ECS_Demo\Mod7Cnt\__projnav\and5or2._sprj Example-2-3\ECS_Demo\Mod7Cnt\__projnav\and5or2_jhdparse_tcl.rsp Example-2-3\ECS_Demo\Mod7Cnt\__projnav\andnor2.xst Example-2-3\ECS_Demo\Mod7Cnt\__projnav\andnor2._sprj Example-2-3\ECS_Demo\Mod7Cnt\__projnav\andnor2_p.xst Example-2-3\ECS_Demo\Mod7Cnt\__projnav\andnor2_p._sprj Example-2-3\ECS_Demo\Mod7Cnt\__projnav\bitgen.rsp Example-2-3\ECS_Demo\Mod7Cnt\__projnav\ednTOngd_tcl.rsp Example-2-3\ECS_Demo\Mod7Cnt\__projnav\fdq.xst Example-2-3\ECS_Demo\Mod7Cnt\__projnav\fdq._sprj Example-2-3\ECS_Demo\Mod7Cnt\__projnav\fdq_jhdparse_tcl.rsp Example-2-3\ECS_Demo\Mod7Cnt\__projnav\map.log Example-2-3\ECS_Demo\Mod7Cnt\__projnav\mod7cnt.gfl Example-2-3\ECS_Demo\Mod7Cnt\__projnav\mod7cnt_flowplus.gfl Example-2-3\ECS_Demo\Mod7Cnt\__projnav\mode7cnt.xst Example-2-3\ECS_Demo\Mod7Cnt\__projnav\mode7cnt._prj Example-2-3\ECS_Demo\Mod7Cnt\__projnav\mode7cnt._sprj Example-2-3\ECS_Demo\Mod7Cnt\__projnav\mode7cnt_jhdparse_tcl.rsp Example-2-3\ECS_Demo\Mod7Cnt\__projnav\mode7cnt_ncdTOut_tcl.rsp Example-2-3\ECS_Demo\Mod7Cnt\__projnav\nc1TOncd_tcl.rsp Example-2-3\ECS_Demo\Mod7Cnt\__projnav\par.log Example-2-3\ECS_Demo\Mod7Cnt\__projnav\posttrc.log Example-2-3\ECS_Demo\Mod7Cnt\__projnav\runXst_tcl.rsp Example-2-3\ECS_Demo\Mod7Cnt\__projnav\xst_sprjTOstx_tcl.rsp Example-2-3\ECS_Demo\Mod7Cnt\__projnav Example-2-3\ECS_Demo\Mod7Cnt\__projnav.log Example-2-3\ECS_Demo\Mod7Cnt Example-2-3\ECS_Demo\Sch\and4or2.sch Example-2-3\ECS_Demo\Sch\and4or2.sym Example-2-3\ECS_Demo\Sch\and5or2.sch Example-2-3\ECS_Demo\Sch\and5or2.sym Example-2-3\ECS_Demo\Sch\fdq.sch Example-2-3\ECS_Demo\Sch\fdq.sym Example-2-3\ECS_Demo\Sch\Mod7Adder.vsd Example-2-3\ECS_Demo\Sch\mode7cnt.sch Example-2-3\ECS_Demo\Sch\mode7cnt.sym Example-2-3\ECS_Demo\Sch Example-2-3\ECS_Demo Example-2-3\示例说明.doc Example-2-3 Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\automake.log Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\bitgen.ut Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\core.tpl Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\coregen.log Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\dpram_core.asy Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\dpram_core.edn Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\dpram_core.jhd Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\dpram_core.ngo Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\dpram_core.sym Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\dpram_core.v Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\dpram_core.veo Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\dpram_core.vhd Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\dpram_core.vho Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\dpram_core.xco Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\dpram_core.xcp Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\DPRAM_core_Demo.npl Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\dpram_core_flist.txt Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\test_fixture.jhd Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\test_fixture.tf Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\test_wave.ant Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\test_wave.jhd Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\test_wave.tbw Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\test_wave.tfw Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.ana Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.bgn Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.bit Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.bld Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.cmd_log Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.dly Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.drc Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.fse Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.jhd Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.log Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.mrp Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.nc1 Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.ncd Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.ncf Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.ngc Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.ngd Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.ngm Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.ngr Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.pad Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.par Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.pcf Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.plg Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.prj Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.sdc Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.sprj Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.srd Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.stx Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.syr Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.tlg Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.twr Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.twx Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.ut Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.v Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top.xpi Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top_map.ncd Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top_map.ngm Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\top_ngdbuild.nav Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\UCF_Demo.cel Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\UCF_Demo.ucf Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\UCF_Demo.ucf.untf Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\userlang.tpl Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\_ngo\dpram_core.ngo Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\_ngo\netlist.lst Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\_ngo Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\_tmp_\coretmpdir Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\_tmp_ Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\__projnav\bitgen.rsp Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\__projnav\dpram_core_demo.gfl Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\__projnav\dpram_core_demo_flowplus.gfl Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\__projnav\ednTOngd_tcl.rsp Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\__projnav\hb_cmds Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\__projnav\map.log Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\__projnav\nc1TOncd_tcl.rsp Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\__projnav\par.log Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\__projnav\parentAssignPackagePinsApp_tcl.rsp Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\__projnav\posttrc.log Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\__projnav\runXst_tcl.rsp Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\__projnav\top.xst Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\__projnav\top._prj Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\__projnav\top._sprj Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\__projnav\top_ncdTOut_tcl.rsp Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\__projnav\__top.rsp Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\__projnav Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo\__projnav.log Example-2-4\CoreGenDemo_DPRAM\DPRAM_core_Demo Example-2-4\CoreGenDemo_DPRAM Example-2-4\示例说明.doc Example-2-4 Example-2-5\HDLBencher_ALU\alu_vlog\alu.edn Example-2-5\HDLBencher_ALU\alu_vlog\alu.fse Example-2-5\HDLBencher_ALU\alu_vlog\ALU.jhd Example-2-5\HDLBencher_ALU\alu_vlog\alu.ldo Example-2-5\HDLBencher_ALU\alu_vlog\alu.log Example-2-5\HDLBencher_ALU\alu_vlog\alu.ncf Example-2-5\HDLBencher_ALU\alu_vlog\alu.plg Example-2-5\HDLBencher_ALU\alu_vlog\alu.prj Example-2-5\HDLBencher_ALU\alu_vlog\alu.sdc Example-2-5\HDLBencher_ALU\alu_vlog\alu.spl Example-2-5\HDLBencher_ALU\alu_vlog\alu.srd Example-2-5\HDLBencher_ALU\alu_vlog\alu.srm Example-2-5\HDLBencher_ALU\alu_vlog\alu.srr Example-2-5\HDLBencher_ALU\alu_vlog\alu.srs Example-2-5\HDLBencher_ALU\alu_vlog\alu.sym Example-2-5\HDLBencher_ALU\alu_vlog\alu.tfi Example-2-5\HDLBencher_ALU\alu_vlog\alu.tlg Example-2-5\HDLBencher_ALU\alu_vlog\ALU.V Example-2-5\HDLBencher_ALU\alu_vlog\alu_compile.tcl Example-2-5\HDLBencher_ALU\alu_vlog\alu_map.tcl Example-2-5\HDLBencher_ALU\alu_vlog\alu_tst_wave.ant Example-2-5\HDLBencher_ALU\alu_vlog\alu_tst_wave.fdo Example-2-5\HDLBencher_ALU\alu_vlog\alu_tst_wave.jhd Example-2-5\HDLBencher_ALU\alu_vlog\alu_tst_wave.tbw Example-2-5\HDLBencher_ALU\alu_vlog\alu_tst_wave.tfw Example-2-5\HDLBencher_ALU\alu_vlog\alu_tst_wave.udo Example-2-5\HDLBencher_ALU\alu_vlog\alu_vlog.npl Example-2-5\HDLBencher_ALU\alu_vlog\alu_vlog.ptf Example-2-5\HDLBencher_ALU\alu_vlog\alu_vlog_syn1\ALU.edf Example-2-5\HDLBencher_ALU\alu_vlog\alu_vlog_syn1\ALU.fse Example-2-5\HDLBencher_ALU\alu_vlog\alu_vlog_syn1\ALU.ncf Example-2-5\HDLBencher_ALU\alu_vlog\alu_vlog_syn1\ALU.plg Example-2-5\HDLBencher_ALU\alu_vlog\alu_vlog_syn1\ALU.srd Example-2-5\HDLBencher_ALU\alu_vlog\alu_vlog_syn1\ALU.srm Example-2-5\HDLBencher_ALU\alu_vlog\alu_vlog_syn1\ALU.srr Example-2-5\HDLBencher_ALU\alu_vlog\alu_vlog_syn1\ALU.srs Example-2-5\HDLBencher_ALU\alu_vlog\alu_vlog_syn1\ALU.tlg Example-2-5\HDLBencher_ALU\alu_vlog\alu_vlog_syn1\syntax.log Example-2-5\HDLBencher_ALU\alu_vlog\alu_vlog_syn1 Example-2-5\HDLBencher_ALU\alu_vlog\alu_vlog_synpro.prd Example-2-5\HDLBencher_ALU\alu_vlog\alu_vlog_synpro.prj Example-2-5\HDLBencher_ALU\alu_vlog\automake.log Example-2-5\HDLBencher_ALU\alu_vlog\HDL_DEMO.V Example-2-5\HDLBencher_ALU\alu_vlog\results.txt Example-2-5\HDLBencher_ALU\alu_vlog\stdout.log Example-2-5\HDLBencher_ALU\alu_vlog\transcript Example-2-5\HDLBencher_ALU\alu_vlog\userlang.tpl Example-2-5\HDLBencher_ALU\alu_vlog\vsim.wlf Example-2-5\HDLBencher_ALU\alu_vlog\work\alu\verilog.asm Example-2-5\HDLBencher_ALU\alu_vlog\work\alu\_primary.dat Example-2-5\HDLBencher_ALU\alu_vlog\work\alu\_primary.vhd Example-2-5\HDLBencher_ALU\alu_vlog\work\alu Example-2-5\HDLBencher_ALU\alu_vlog\work\glbl\verilog.asm Example-2-5\HDLBencher_ALU\alu_vlog\work\glbl\_primary.dat Example-2-5\HDLBencher_ALU\alu_vlog\work\glbl\_primary.vhd Example-2-5\HDLBencher_ALU\alu_vlog\work\glbl Example-2-5\HDLBencher_ALU\alu_vlog\work\hdl_demo\verilog.asm Example-2-5\HDLBencher_ALU\alu_vlog\work\hdl_demo\_primary.dat Example-2-5\HDLBencher_ALU\alu_vlog\work\hdl_demo\_primary.vhd Example-2-5\HDLBencher_ALU\alu_vlog\work\hdl_demo Example-2-5\HDLBencher_ALU\alu_vlog\work\testbench\verilog.asm Example-2-5\HDLBencher_ALU\alu_vlog\work\testbench\_primary.dat Example-2-5\HDLBencher_ALU\alu_vlog\work\testbench\_primary.vhd Example-2-5\HDLBencher_ALU\alu_vlog\work\testbench Example-2-5\HDLBencher_ALU\alu_vlog\work\_info Example-2-5\HDLBencher_ALU\alu_vlog\work Example-2-5\HDLBencher_ALU\alu_vlog\__projnav\alu.ise_created Example-2-5\HDLBencher_ALU\alu_vlog\__projnav\ALU_jhdparse_tcl.rsp Example-2-5\HDLBencher_ALU\alu_vlog\__projnav\alu_tst_wave_createfdo.rsp Example-2-5\HDLBencher_ALU\alu_vlog\__projnav\alu_vlog.gfl Example-2-5\HDLBencher_ALU\alu_vlog\__projnav\jhdparse.log Example-2-5\HDLBencher_ALU\alu_vlog\__projnav\vTOldo_tcl.rsp Example-2-5\HDLBencher_ALU\alu_vlog\__projnav\__synProj.rsp Example-2-5\HDLBencher_ALU\alu_vlog\__projnav Example-2-5\HDLBencher_ALU\alu_vlog\__projnav.log Example-2-5\HDLBencher_ALU\alu_vlog Example-2-5\HDLBencher_ALU\源文件\ALU.V Example-2-5\HDLBencher_ALU\源文件\alu_tst_wave.tbw Example-2-5\HDLBencher_ALU\源文件\HDL_DEMO.V Example-2-5\HDLBencher_ALU\源文件 Example-2-5\HDLBencher_ALU Example-2-5\示例说明.doc Example-2-5