文件名称:DDSFPGA_cylone
介绍说明－－下载内容均来自于网络，请自行研究使用
dds设计，花了一个星期做的,verilog写的，可生成多种波形，频率范围可上M,性能不错。-dds design, spent a week doing, verilog written, multiple waveform generation, frequency range available on the M, good performance.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
压缩包 : 29782170ddsfpga_cylone.rar 列表 DDSFPGA\creat.c DDSFPGA\512.mif DDSFPGA\DDSFPGA.qpf DDSFPGA\DDSFPGA.qsf DDSFPGA\db\DDSFPGA.db_info DDSFPGA\db\DDSFPGA.(0).cnf.cdb DDSFPGA\db\DDSFPGA.(0).cnf.hdb DDSFPGA\db\DDSFPGA.rtlv_sg_swap.cdb DDSFPGA\db\DDSFPGA.fit.qmsg DDSFPGA\db\DDSFPGA.cmp.cdb DDSFPGA\db\DDSFPGA.(1).cnf.cdb DDSFPGA\db\DDSFPGA.map.qmsg DDSFPGA\db\DDSFPGA.smp_dump.txt DDSFPGA\db\DDSFPGA.(8).cnf.cdb DDSFPGA\db\DDSFPGA.(8).cnf.hdb DDSFPGA\db\DDSFPGA.asm.qmsg DDSFPGA\db\DDSFPGA.syn_hier_info DDSFPGA\db\DDSFPGA.(2).cnf.cdb DDSFPGA\db\DDSFPGA.tan.qmsg DDSFPGA\db\DDSFPGA.sim.qmsg DDSFPGA\db\DDSFPGA.(10).cnf.cdb DDSFPGA\db\DDSFPGA.sim.hdb DDSFPGA\db\DDSFPGA.(3).cnf.cdb DDSFPGA\db\DDSFPGA.pre_map.hdb DDSFPGA\db\DDSFPGA.(1).cnf.hdb DDSFPGA\db\DDSFPGA.(2).cnf.hdb DDSFPGA\db\DDSFPGA.sim.vwf DDSFPGA\db\DDSFPGA.(3).cnf.hdb DDSFPGA\db\DDSFPGA.sim.rdb DDSFPGA\db\DDSFPGA.cbx.xml DDSFPGA\db\DDSFPGA_cmp.qrpt DDSFPGA\db\DDSFPGA.(9).cnf.cdb DDSFPGA\db\DDSFPGA.(9).cnf.hdb DDSFPGA\db\DDSFPGA.(4).cnf.cdb DDSFPGA\db\DDSFPGA.pre_map.cdb DDSFPGA\db\DDSFPGA.eds_overflow DDSFPGA\db\DDSFPGA.rtlv.hdb DDSFPGA\db\DDSFPGA.map.cdb DDSFPGA\db\DDSFPGA_sim.qrpt DDSFPGA\db\DDSFPGA.(10).cnf.hdb DDSFPGA\db\DDSFPGA.sgdiff.hdb DDSFPGA\db\DDSFPGA.eco.cdb DDSFPGA\db\DDSFPGA.(4).cnf.hdb DDSFPGA\db\DDSFPGA.map.hdb DDSFPGA\db\DDSFPGA.rtlv_sg.cdb DDSFPGA\db\DDSFPGA.sgdiff.cdb DDSFPGA\db\DDSFPGA.signalprobe.cdb DDSFPGA\db\DDSFPGA.cmp.tdb DDSFPGA\db\DDSFPGA.sld_design_entry_dsc.sci DDSFPGA\db\DDSFPGA.cmp.hdb DDSFPGA\db\DDSFPGA.cmp.rdb DDSFPGA\db\DDSFPGA.cmp0.ddb DDSFPGA\db\DDSFPGA.sld_design_entry.sci DDSFPGA\db\DDSFPGA.hif DDSFPGA\db\DDSFPGA.(5).cnf.cdb DDSFPGA\db\DDSFPGA.(5).cnf.hdb DDSFPGA\db\altsyncram_88s.tdf DDSFPGA\db\DDSFPGA.(6).cnf.cdb DDSFPGA\db\DDSFPGA.(6).cnf.hdb DDSFPGA\db\DDSFPGA.(7).cnf.cdb DDSFPGA\db\DDSFPGA.(7).cnf.hdb DDSFPGA\db\DDSFPGA.hier_info DDSFPGA\db\DDSFPGA.psp DDSFPGA\db DDSFPGA\romlookup.v DDSFPGA\romlookup_bb.v DDSFPGA\DDSFPGA.done DDSFPGA\DDSFPGA.bdf DDSFPGA\DDSFPGA.qws DDSFPGA\cmp_state.ini DDSFPGA\DDSFPGA.map.rpt DDSFPGA\DDSFPGA.flow.rpt DDSFPGA\DDSFPGA.map.summary DDSFPGA\squwave.bsf DDSFPGA\Key.bsf DDSFPGA\squwave.v.bak DDSFPGA\triawave.v.bak DDSFPGA\control.v.bak DDSFPGA\triawave.bsf DDSFPGA\creat.exe DDSFPGA\1024.mif DDSFPGA\romlookup.bsf DDSFPGA\control.bsf DDSFPGA\datachoose.bsf DDSFPGA\DDSFPGA.map.eqn DDSFPGA\DDSFPGA.fit.eqn DDSFPGA\DDSFPGA.pin DDSFPGA\DDSFPGA.fit.rpt DDSFPGA\DDSFPGA.fit.summary DDSFPGA\DDSFPGA.sof DDSFPGA\DDSFPGA.pof DDSFPGA\DDSFPGA.asm.rpt DDSFPGA\DDSFPGA.tan.summary DDSFPGA\DDSFPGA.tan.rpt DDSFPGA\DDSFPGA.vwf DDSFPGA\DDSFPGA.sim.rpt DDSFPGA\datachoose.v DDSFPGA\clock_d2.v DDSFPGA\clock_d2.bsf DDSFPGA\triawave.v DDSFPGA\squwave.v DDSFPGA\control.v DDSFPGA\key.v DDSFPGA