文件名称:9.1_ONE_PULSE
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基于Verilog-HDL的硬件电路的实现
9.1 简单的可编程单脉冲发生器
9.1.1 由系统功能描述时序关系
9.1.2 流程图的设计
9.1.3 系统功能描述
9.1.4 逻辑框图
9.1.5 延时模块的详细描述及仿真
9.1.6 功能模块Verilog-HDL描述的模块化方法
9.1.7 输入检测模块的详细描述及仿真
9.1.8 计数模块的详细描述
9.1.9 可编程单脉冲发生器的系统仿真
9.1.10 可编程单脉冲发生器的硬件实现
9.1.11 关于电路设计中常用的几个有关名词
-based on Verilog-HDL hardware Circuit of 9.1 simple programmable pulse generator 9.1.1 system functions described by the temporal flow chart 9.1.2 9.1.3 System Design Descr iption logic diagram 9.1.5 9.1.4 Delay Module detailed descr iption and simulation of 9.1. 6 functional modules Verilog-HDL descr iption of the modular input method detection module 9.1.7 detailed 9.1.8 Descr iption and Simulation module counting a detailed descr iption 9.1.9 programmable pulse generator system 9.1.10 Simulation programmable pulse generator hardware on the circuit design 9.1.11 Constant Some of the terminology
9.1 简单的可编程单脉冲发生器
9.1.1 由系统功能描述时序关系
9.1.2 流程图的设计
9.1.3 系统功能描述
9.1.4 逻辑框图
9.1.5 延时模块的详细描述及仿真
9.1.6 功能模块Verilog-HDL描述的模块化方法
9.1.7 输入检测模块的详细描述及仿真
9.1.8 计数模块的详细描述
9.1.9 可编程单脉冲发生器的系统仿真
9.1.10 可编程单脉冲发生器的硬件实现
9.1.11 关于电路设计中常用的几个有关名词
-based on Verilog-HDL hardware Circuit of 9.1 simple programmable pulse generator 9.1.1 system functions described by the temporal flow chart 9.1.2 9.1.3 System Design Descr iption logic diagram 9.1.5 9.1.4 Delay Module detailed descr iption and simulation of 9.1. 6 functional modules Verilog-HDL descr iption of the modular input method detection module 9.1.7 detailed 9.1.8 Descr iption and Simulation module counting a detailed descr iption 9.1.9 programmable pulse generator system 9.1.10 Simulation programmable pulse generator hardware on the circuit design 9.1.11 Constant Some of the terminology
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压缩包 : 1052302859.1_one_pulse.rar 列表 09-01_fangzhen\ONE_PULSE.v 09-01_fangzhen\ONE_PULSE_TEST.v 09-01_fangzhen\P_DETECT.v 09-01_fangzhen\P_DETECT_TEST.v 09-01_fangzhen\P_DLY_1.v 09-01_fangzhen\P_DLY_2.v 09-01_fangzhen\P_DLY_1_TEST.v 09-01_fangzhen\P_DLY_2_TEST.v 09-01_fangzhen