文件名称:labsolutions
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Xilinx的培训教程的源码 virtex-Xilinx training guides source virtex
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压缩包 : 101259385labsolutions.zip 列表 labsolutions/ labsolutions/verilog/ labsolutions/verilog/lab1/ labsolutions/verilog/lab1/Assembler/ labsolutions/verilog/lab1/Assembler/CONSTANT.TXT labsolutions/verilog/lab1/Assembler/INT_TEST.COE labsolutions/verilog/lab1/Assembler/INT_TEST.DEC labsolutions/verilog/lab1/Assembler/INT_TEST.FMT labsolutions/verilog/lab1/Assembler/INT_TEST.HEX labsolutions/verilog/lab1/Assembler/INT_TEST.LOG labsolutions/verilog/lab1/Assembler/INT_TEST.M labsolutions/verilog/lab1/Assembler/int_test.psm labsolutions/verilog/lab1/Assembler/INT_TEST.V labsolutions/verilog/lab1/Assembler/INT_TEST.VHD labsolutions/verilog/lab1/Assembler/KCPSM3.EXE labsolutions/verilog/lab1/Assembler/LABELS.TXT labsolutions/verilog/lab1/Assembler/PASS1.DAT labsolutions/verilog/lab1/Assembler/PASS2.DAT labsolutions/verilog/lab1/Assembler/PASS3.DAT labsolutions/verilog/lab1/Assembler/PASS4.DAT labsolutions/verilog/lab1/Assembler/PASS5.DAT labsolutions/verilog/lab1/Assembler/ROM_form.coe labsolutions/verilog/lab1/Assembler/ROM_form.v labsolutions/verilog/lab1/Assembler/ROM_form.vhd labsolutions/verilog/lab1/Assembler/UCLOCK.COE labsolutions/verilog/lab1/Assembler/UCLOCK.DEC labsolutions/verilog/lab1/Assembler/UCLOCK.FMT labsolutions/verilog/lab1/Assembler/UCLOCK.HEX labsolutions/verilog/lab1/Assembler/UCLOCK.LOG labsolutions/verilog/lab1/Assembler/UCLOCK.M labsolutions/verilog/lab1/Assembler/uclock.psm labsolutions/verilog/lab1/Assembler/UCLOCK.V labsolutions/verilog/lab1/Assembler/UCLOCK.VHD labsolutions/verilog/lab1/Flow_Lab/ labsolutions/verilog/lab1/Flow_Lab/Flow_Lab.ise labsolutions/verilog/lab1/Flow_Lab/Flow_Lab.ise_8.1i_backup labsolutions/verilog/lab1/Flow_Lab/Flow_Lab.ise_ISE_Backup labsolutions/verilog/lab1/Flow_Lab/Flow_Lab.ntrc_log labsolutions/verilog/lab1/Flow_Lab/INT_TEST.V labsolutions/verilog/lab1/Flow_Lab/isim.hdlsourcefiles labsolutions/verilog/lab1/Flow_Lab/isim.log labsolutions/verilog/lab1/Flow_Lab/isim.tmp_save/ labsolutions/verilog/lab1/Flow_Lab/isim.tmp_save/_1 labsolutions/verilog/lab1/Flow_Lab/isimwavedata.xwv labsolutions/verilog/lab1/Flow_Lab/kcpsm3.v labsolutions/verilog/lab1/Flow_Lab/kcpsm3_int_test.v labsolutions/verilog/lab1/Flow_Lab/kcpsm3_int_test_prev_built.ngd labsolutions/verilog/lab1/Flow_Lab/kcpsm3_int_test_summary.html labsolutions/verilog/lab1/Flow_Lab/kcpsm3_int_test_vhdl.prj labsolutions/verilog/lab1/Flow_Lab/testbench.v labsolutions/verilog/lab1/Flow_Lab/testbench_beh.prj labsolutions/verilog/lab1/Flow_Lab/testbench_isim_beh.exe labsolutions/verilog/lab1/Flow_Lab/_xmsgs/ labsolutions/verilog/lab1/Flow_Lab/_xmsgs/fuse.xmsgs labsolutions/verilog/lab1/Flow_Lab/__ISE_repository_Flow_Lab.ise_.lock labsolutions/verilog/lab2/ labsolutions/verilog/lab2/arwz_pace.dhp labsolutions/verilog/lab2/arwz_pace.ise labsolutions/verilog/lab2/arwz_pace.ise.old labsolutions/verilog/lab2/arwz_pace.ise_8.1i_backup labsolutions/verilog/lab2/arwz_pace.ise_ISE_Backup labsolutions/verilog/lab2/arwz_pace.ntrc_log labsolutions/verilog/lab2/bbfifo_16x8.v labsolutions/verilog/lab2/kcpsm3.v labsolutions/verilog/lab2/kcuart_rx.v labsolutions/verilog/lab2/kcuart_tx.v labsolutions/verilog/lab2/my_dcm.xaw labsolutions/verilog/lab2/Project.dhp labsolutions/verilog/lab2/transcript labsolutions/verilog/lab2/uart_clock.ucf labsolutions/verilog/lab2/uart_clock.ut labsolutions/verilog/lab2/uart_clock.v labsolutions/verilog/lab2/uart_clock_prev_built.ngd labsolutions/verilog/lab2/uart_clock_summary.html labsolutions/verilog/lab2/uart_clock_usage.xml labsolutions/verilog/lab2/uart_clock_vhdl.prj labsolutions/verilog/lab2/uart_rx.v labsolutions/verilog/lab2/uart_rx_summary.html labsolutions/verilog/lab2/uart_tx.v labsolutions/verilog/lab2/UCLOCK.V labsolutions/verilog/lab2/_impact.cmd labsolutions/verilog/lab2/_impact.log labsolutions/verilog/lab2/_pace.ucf labsolutions/verilog/lab2/_xmsgs/ labsolutions/verilog/lab2/__ISE_repository_arwz_pace.ise_.lock labsolutions/verilog/lab3/ labsolutions/verilog/lab3/Assembler/ labsolutions/verilog/lab3/Assembler/assemble.bat labsolutions/verilog/lab3/Assembler/CONSTANT.TXT labsolutions/verilog/lab3/Assembler/KCPSM3.EXE labsolutions/verilog/lab3/Assembler/LABELS.TXT labsolutions/verilog/lab3/Assembler/PASS1.DAT labsolutions/verilog/lab3/Assembler/PASS2.DAT labsolutions/verilog/lab3/Assembler/PASS3.DAT labsolutions/verilog/lab3/Assembler/PASS4.DAT labsolutions/verilog/lab3/Assembler/PASS5.DAT labsolutions/verilog/lab3/Assembler/PROGRAM.COE labsolutions/verilog/lab3/Assembler/PROGRAM.DEC labsolutions/verilog/lab3/Assembler/PROGRAM.FMT labsolutions/verilog/lab3/Assembler/PROGRAM.HEX labsolutions/verilog/lab3/Assembler/PROGRAM.LOG labsolutions/verilog/lab3/Assembler/PROGRAM.M labsolutions/verilog/lab3/Assembler/program.psm labsolutions/verilog/lab3/Assembler/PROGRAM.V labsolutions/verilog/lab3/Assembler/PROGRAM.VHD labsolutions/verilog/lab3/Assembler/ROM_form.coe labsolutions/verilog/lab3/Assembler/ROM_form.v labsolutions/verilog/lab3/Assembler/ROM_form.vhd labsolutions/verilog/lab3/Assembler/transcript labsolutions/verilog/lab3/loopback.v labsolutions/verilog/lab3/testbench.v labsolutions/verilog/lab3/time_const/ labsolutions/verilog/lab3/time_const/bbfifo_16x8.v labsolutions/verilog/lab3/time_const/isim.hdlsourcefiles labsolutions/verilog/lab3/time_const/isim.log labsolutions/verilog/lab3/time_const/isim.tmp_save/ labsolutions/verilog/lab3/time_const/isim.tmp_save/_1 labsolutions/verilog/lab3/time_const/isimwavedata.xwv labsolutions/verilog/lab3/time_const/kcpsm3.v labsolutions/verilog/lab3/time_const/kcuart_rx.v labsolutions/verilog/lab3/time_const/kcuart_tx.v labsolutions/verilog/lab3/time_const/lab3.cfi labsolutions/verilog/lab3/time_const/lab3.mcs labsolutions/verilog/lab3/time_const/lab3.prm labsolutions/verilog/lab3/time_const/lab3.sig labsolutions/verilog/lab3/time_const/loopback.bgn labsolutions/verilog/lab3/time_const/loopback.bit labsolutions/verilog/lab3/time_const/loopback.bld labsolutions/verilog/lab3/time_const/loopback.cel labsolutions/verilog/lab3/time_const/loopback.cmd_log labsolutions/verilog/lab3/time_const/loopback.lso labsolutions/verilog/lab3/time_const/loopback.mrp labsolutions/verilog/lab3/time_const/loopback.ncd labsolutions/verilog/lab3/time_const/loopback.ngc labsolutions/verilog/lab3/time_const/loopback.ngd labsolutions/verilog/lab3/time_const/loopback.ngm labsolutions/verilog/lab3/time_const/loopback.ngr labsolutions/verilog/lab3/time_const/loopback.pad labsolutions/verilog/lab3/time_const/loopback.par labsolutions/verilog/lab3/time_const/loopback.pcf labsolutions/verilog/lab3/time_const/loopback.prj labsolutions/verilog/lab3/time_const/loopback.stx labsolutions/verilog/lab3/time_const/loopback.syr labsolutions/verilog/lab3/time_const/loopback.ucf labsolutions/verilog/lab3/time_const/loopback.unroutes labsolutions/verilog/lab3/time_const/loopback.ut labsolutions/verilog/lab3/time_const/loopback.v labsolutions/verilog/lab3/time_const/loopback.xpi labsolutions/verilog/lab3/time_const/loopback.xst labsolutions/verilog/lab3/time_const/loopback_last_par.ncd labsolutions/verilog/lab3/time_const/loopback_pad.csv labsolutions/verilog/lab3/time_const/loopback_pad.txt labsolutions/verilog/lab3/time_const/loopback_summary.html labsolutions/verilog/lab3/time_const/loopback_testbench_v_tf_isim_beh.exe labsolutions/verilog/lab3/time_const/loopback_usage.xml labsolutions/verilog/lab3/time_const/loopback_vhdl.prj labsolutions/verilog/lab3/time_const/my_dcm.v labsolutions/verilog/lab3/time_const/my_dcm.xaw labsolutions/verilog/lab3/time_const/my_dcm_arwz.ucf labsolutions/verilog/lab3/time_const/netlist.lst labsolutions/verilog/lab3/time_const/prjname.lso labsolutions/verilog/lab3/time_const/time_const.ipf labsolutions/verilog/lab3/time_const/time_const.ipf_8.1i_backup labsolutions/verilog/lab3/time_const/time_const.ipf_ISE_Backup labsolutions/verilog/lab3/time_const/time_const.ise labsolutions/verilog/lab3/time_const/time_const.ise_8.1i_backup labsolutions/verilog/lab3/time_const/time_const.ise_ISE_Backup labsolutions/verilog/lab3/time_const/time_const.ntrc_log labsolutions/verilog/lab3/time_const/Timing1.twx labsolutions/verilog/lab3/time_const/uart_rx.v labsolutions/verilog/lab3/time_const/uart_tx.v labsolutions/verilog/lab3/time_const/xaw2verilog.log labsolutions/verilog/lab3/time_const/xst/ labsolutions/verilog/lab3/time_const/xst/dump.xst/ labsolutions/verilog/lab3/time_const/xst/dump.xst/loopback.prj/ labsolutions/verilog/lab3/time_const/xst/dump.xst/loopback.prj/ngx/ labsolutions/verilog/lab3/time_const/xst/dump.xst/loopback.prj/ngx/notopt/ labsolutions/verilog/lab3/time_const/xst/dump.xst/loopback.prj/ngx/opt/ labsolutions/verilog/lab3/time_const/xst/dump.xst/loopback.prj/ntrc.scr labsolutions/verilog/lab3/time_const/xst/projnav.tmp/ labsolutions/verilog/lab3/time_const/xst/work/ labsolutions/verilog/lab3/time_const/xst/work/hdllib.ref labsolutions/verilog/lab3/time_const/xst/work/vlg13/ labsolutions/verilog/lab3/time_const/xst/work/vlg13/kcuart__rx.bin labsolutions/verilog/lab3/time_const/xst/work/vlg19/ labsolutions/verilog/lab3/time_const/xst/work/vlg19/kcpsm3.bin labsolutions/verilog/lab3/time_const/xst/work/vlg1D/ labsolutions/verilog/lab3/time_const/xst/work/vlg1D/kcuart__tx.bin labsolutions/verilog/lab3/time_const/xst/work/vlg21/ labsolutions/verilog/lab3/time_const/xst/work/vlg21/uart__rx.bin labsolutions/verilog/lab3/time_const/xst/work/vlg2B/ labsolutions/verilog/lab3/time_const/xst/work/vlg2B/uart__tx.bin labsolutions/verilog/lab3/time_const/xst/work/vlg48/ labsolutions/verilog/lab3/time_const/xst/work/vlg48/program.bin labsolutions/verilog/lab3/time_const/xst/work/vlg5A/ labsolutions/verilog/lab3/time_const/xst/work/vlg5A/bbfifo__16x8.bin labsolutions/verilog/lab3/time_const/xst/work/vlg7B/ labsolutions/verilog/lab3/time_const/xst/work/vlg7B/loopback.bin labsolutions/verilog/lab3/time_const/xst/work/vlg7D/ labsolutions/verilog/lab3/time_const/xst/work/vlg7D/my__dcm.bin labsolutions/verilog/lab3/time_const/_impact.cmd labsolutions/verilog/lab3/time_const/_impact.log labsolutions/verilog/lab3/time_const/_impactbatch.log labsolutions/verilog/lab3/time_const/_xmsgs/ labsolutions/verilog/lab3/time_const/_xmsgs/bitgen.xmsgs labsolutions/verilog/lab3/time_const/_xmsgs/fuse.xmsgs labsolutions/verilog/lab3/time_const/_xmsgs/map.xmsgs labsolutions/verilog/lab3/time_const/_xmsgs/netgen.xmsgs labsolutions/verilog/lab3/time_const/_xmsgs/ngdbuild.xmsgs labsolutions/verilog/lab3/time_const/_xmsgs/par.xmsgs labsolutions/verilog/lab3/time_const/_xmsgs/trce.xmsgs labsolutions/verilog/lab3/time_const/_xmsgs/xst.xmsgs labsolutions/verilog/lab3/time_const/__ISE_repository_time_const.ise_.lock labsolutions/verilog/lab4/ labsolutions/verilog/lab4/Assembler/ labsolutions/verilog/lab4/Assembler/CONSTANT.TXT labsolutions/verilog/lab4/Assembler/KCPSM3.EXE labsolutions/verilog/lab4/Assembler/LABELS.TXT labsolutions/verilog/lab4/Assembler/PASS1.DAT labsolutions/verilog/lab4/Assembler/PASS2.DAT labsolutions/verilog/lab4/Assembler/PASS3.DAT labsolutions/verilog/lab4/Assembler/PASS4.DAT labsolutions/verilog/lab4/Assembler/PASS5.DAT labsolutions/verilog/lab4/Assembler/PROGRAM.COE labsolutions/verilog/lab4/Assembler/PROGRAM.DEC labsolutions/verilog/lab4/Assembler/PROGRAM.FMT labsolutions/verilog/lab4/Assembler/PROGRAM.HEX labsolutions/verilog/lab4/Assembler/PROGRAM.LOG labsolutions/verilog/lab4/Assembler/PROGRAM.M labsolutions/verilog/lab4/Assembler/program.psm labsolutions/verilog/lab4/Assembler/PROGRAM.V labsolutions/verilog/lab4/Assembler/PROGRAM.VHD labsolutions/verilog/lab4/Assembler/ROM_form.coe labsolutions/verilog/lab4/Assembler/ROM_form.v labsolutions/verilog/lab4/Assembler/ROM_form.vhd labsolutions/verilog/lab4/bbfifo_16x8.v labsolutions/verilog/lab4/kcpsm3.v labsolutions/verilog/lab4/kcuart_rx.v labsolutions/verilog/lab4/kcuart_tx.v labsolutions/verilog/lab4/loopback.ucf labsolutions/verilog/lab4/loopback.ut labsolutions/verilog/lab4/loopback.v labsolutions/verilog/lab4/loopback_last_par.ncd labsolutions/verilog/lab4/loopback_prev_built.ngd labsolutions/verilog/lab4/loopback_summary.html labsolutions/verilog/lab4/loopback_usage.xml labsolutions/verilog/lab4/loopback_vhdl.prj labsolutions/verilog/lab4/my_dcm.xaw labsolutions/verilog/lab4/Project.dhp labsolutions/verilog/lab4/synth_lab.dhp labsolutions/verilog/lab4/synth_lab.ipf labsolutions/verilog/lab4/synth_lab.ipf_8.1i_backup labsolutions/verilog/lab4/synth_lab.ise labsolutions/verilog/lab4/synth_lab.ise.old labsolutions/verilog/lab4/synth_lab.ise_8.1i_backup labsolutions/verilog/lab4/synth_lab.ise_ISE_Backup labsolutions/verilog/lab4/synth_lab.ntrc_log labsolutions/verilog/lab4/uart_rx.v labsolutions/verilog/lab4/uart_tx.v labsolutions/verilog/lab4/_xmsgs/ labsolutions/verilog/lab5/ labsolutions/verilog/lab5/Assembler/ labsolutions/verilog/lab5/Assembler/CONSTANT.TXT labsolutions/verilog/lab5/Assembler/KCPSM3.EXE labsolutions/verilog/lab5/Assembler/LABELS.TXT labsolutions/verilog/lab5/Assembler/PASS1.DAT labsolutions/verilog/lab5/Assembler/PASS2.DAT labsolutions/verilog/lab5/Assembler/PASS3.DAT labsolutions/verilog/lab5/Assembler/PASS4.DAT labsolutions/verilog/lab5/Assembler/PASS5.DAT labsolutions/verilog/lab5/Assembler/PROGRAM.COE labsolutions/verilog/lab5/Assembler/PROGRAM.DEC labsolutions/verilog/lab5/Assembler/PROGRAM.FMT labsolutions/verilog/lab5/Assembler/PROGRAM.HEX labsolutions/verilog/lab5/Assembler/PROGRAM.LOG labsolutions/verilog/lab5/Assembler/PROGRAM.M labsolutions/verilog/lab5/Assembler/program.psm labsolutions/verilog/lab5/Assembler/PROGRAM.V labsolutions/verilog/lab5/Assembler/PROGRAM.VHD labsolutions/verilog/lab5/Assembler/ROM_form.coe labsolutions/verilog/lab5/Assembler/ROM_form.v labsolutions/verilog/lab5/Assembler/ROM_form.vhd labsolutions/verilog/lab5/bbfifo_16x8.v labsolutions/verilog/lab5/blk_mem_gen_ds512.pdf labsolutions/verilog/lab5/blk_mem_gen_release_notes.txt labsolutions/verilog/lab5/coregen_lab.dhp labsolutions/verilog/lab5/coregen_lab.ise labsolutions/verilog/lab5/coregen_lab.ise.old labsolutions/verilog/lab5/coregen_lab.ise_8.1i_backup labsolutions/verilog/lab5/coregen_lab.ise_ISE_Backup labsolutions/verilog/lab5/coregen_lab.ntrc_log labsolutions/verilog/lab5/coregen_lock labsolutions/verilog/lab5/isim.hdlsourcefiles labsolutions/verilog/lab5/isim.log labsolutions/verilog/lab5/isim.tmp_save/ labsolutions/verilog/lab5/isim.tmp_save/_1 labsolutions/verilog/lab5/isimwavedata.xwv labsolutions/verilog/lab5/kcpsm3.v labsolutions/verilog/lab5/kcuart_rx.v labsolutions/verilog/lab5/kcuart_tx.v labsolutions/verilog/lab5/loopback.ucf labsolutions/verilog/lab5/loopback.ut labsolutions/verilog/lab5/loopback.v labsolutions/verilog/lab5/loopback_last_par.ncd labsolutions/verilog/lab5/loopback_prev_built.ngd labsolutions/verilog/lab5/loopback_summary.html labsolutions/verilog/lab5/loopback_vhdl.prj labsolutions/verilog/lab5/my_dcm.xaw labsolutions/verilog/lab5/program.asy labsolutions/verilog/lab5/program.edn labsolutions/verilog/lab5/program.ngc labsolutions/verilog/lab5/program.sym labsolutions/verilog/lab5/program.v labsolutions/verilog/lab5/program.veo labsolutions/verilog/lab5/program.vhd labsolutions/verilog/lab5/program.vho labsolutions/verilog/lab5/program.xco labsolutions/verilog/lab5/program_flist.txt labsolutions/verilog/lab5/Project.dhp labsolutions/verilog/lab5/STD_OUTPUT labsolutions/verilog/lab5/templates/ labsolutions/verilog/lab5/templates/coregen.xml labsolutions/verilog/lab5/terminal.ht labsolutions/verilog/lab5/testbench.v labsolutions/verilog/lab5/tmp/ labsolutions/verilog/lab5/tmp/_cg/ labsolutions/verilog/lab5/tmp/_cg/program.mif labsolutions/verilog/lab5/uart_rx.v labsolutions/verilog/lab5/uart_tx.v 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