文件名称:uart
介绍说明－－下载内容均来自于网络，请自行研究使用
用Verilog HDL编写的串口输入输出程序，可实现数据的传输，在DE2-70上测试通过，有很大的参考价值。-Prepared by the serial input and output using Verilog HDL program can achieve data transmission test by DE2-70, there is a great reference value.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
uart\.metadata\.lock
....\.........\.log
....\.........\.plugins\org.eclipse.cdt.core\.log
....\.........\........\................make.core\specs.c
....\.........\........\.........................\specs.cpp
....\.........\........\.....................ui\dialog_settings.xml
....\.........\........\.............ore.resources\.root\.indexes\history.version
....\.........\........\..........................\.....\........\properties.index
....\.........\........\..........................\.....\........\properties.version
....\.........\........\..........................\.....\2.tree
....\.........\........\..........................\.safetable\org.eclipse.core.resources
....\.........\........\..................untime\.settings\org.eclipse.cdt.debug.core.prefs
....\.........\........\........................\.........\org.eclipse.cdt.ui.prefs
....\.........\........\........................\.........\org.eclipse.core.resources.prefs
....\.........\........\........................\.........\org.eclipse.ui.ide.prefs
....\.........\........\........................\.........\org.eclipse.ui.prefs
....\.........\........\............ui.ide\dialog_settings.xml
....\.........\........\...............workbench\dialog_settings.xml
....\.........\........\........................\workbench.xml
....\.........\version.ini
....\.sopc_builder\filters.xml
....\.............\install.ptf
....\.............\install2.ptf
....\.............\preferences.xml
....\ads_busy.v
....\ads_clk.v
....\ads_cs.v
....\ads_din.v
....\ads_dout.v
....\ads_nirq.v
....\altpllpll.ppf
....\altpllpll.qip
....\altpllpll.v
....\altpllpll_0.ppf
....\altpllpll_0.qip
....\altpllpll_0.v
....\altpllpll_0_bb.v
....\altpllpll_0_wave0.jpg
....\altpllpll_0_waveforms.html
....\altpllpll_bb.v
....\CLK_1549.v
....\cpu.ocp
....\cpu.sdc
....\cpu.v
....\cpu_bht_ram.mif
....\cpu_ic_tag_ram.mif
....\cpu_jtag_debug_module_sysclk.v
....\cpu_jtag_debug_module_tck.v
....\cpu_jtag_debug_module_wrapper.v
....\cpu_mult_cell.v
....\cpu_ociram_default_contents.mif
....\cpu_oci_test_bench.v
....\cpu_rf_ram_a.mif
....\cpu_rf_ram_b.mif
....\cpu_test_bench.v
....\cs.v
....\CS_1549.v
....\data.v
....\DATA_1549.v
....\db\altsyncram_9tl1.tdf
....\..\altsyncram_e502.tdf
....\..\altsyncram_ij21.tdf
....\..\altsyncram_p2f1.tdf
....\..\altsyncram_pkf1.tdf
....\..\altsyncram_q2f1.tdf
....\..\altsyncram_qed1.tdf
....\..\altsyncram_t072.tdf
....\..\altsyncram_u0g1.tdf
....\..\a_dpfifo_8t21.tdf
....\..\a_fefifo_7cf.tdf
....\..\cntr_fjb.tdf
....\..\cntr_rj7.tdf
....\..\ded_mult_2o81.tdf
....\..\dffpipe_93c.tdf
....\..\dpram_5h21.tdf
....\..\mult_add_4cr2.tdf
....\..\mult_add_6cr2.tdf
....\..\prev_cmp_sunnyuart.asm.qmsg
....\..\prev_cmp_sunnyuart.fit.qmsg
....\..\prev_cmp_sunnyuart.map.qmsg
....\..\prev_cmp_sunnyuart.qmsg
....\..\prev_cmp_sunnyuart.tan.qmsg
....\..\scfifo_1n21.tdf
....\..\sunnyuart.asm.qmsg
....\..\sunnyuart.asm_labs.ddb
....\..\sunnyuart.cbx.xml
....\..\sunnyuart.cmp.bpm
....\..\sunnyuart.cmp.cdb
....\..\sunnyuart.cmp.ecobp
....\..\sunnyuart.cmp.hdb
....\..\sunnyuart.cmp.kpt
....\..\sunnyuart.cmp.logdb
....\..\sunnyuart.cmp.rdb
....\..\sunnyuart.cmp.tdb
....\..\sunnyuart.cmp0.ddb
....\..\sunnyuart.cmp_merge.kpt
....\..\sunnyuart.db_info
....\..\sunnyuart.eco.cdb
....\..\sunnyuart.fit.qmsg
....\..\sunnyuart.hier_info