文件名称:design_5
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将48M时钟信号分频为1Khz信号,并由dig(2:0)输出。因为实验板的七段译码显示器均公用同一数据线,所以必须提供一个较快的扫描信号(由于人的视觉停留,这个扫描信号必须要大于20hz,系统设计中用的是1Khz)通过扫描将选手号和抢答倒计时和答题倒计时显示分时显示在不同的七段译码显示器上,此系统中用dig(2:0)三位通过3_8译码器分时选3个七段译码显示器。-48M clock signal divider 1Khz signal by the output of the dig (2:0). Because the test board seven segment decoder monitors are common the same data line, must be provided to a fast scan signal (due to the stay of the human visual scanning signal must be greater than 20Hz, the system design is used 1Khz) by scanning player number and answer in the countdown and answer countdown display timeshare displayed on the seven-segment decoder displays with this system dig (2:0) three by 3_8 decoder timeshare elect three seven segment decoder monitor.
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5基于FPGA的扫描器设计和仿真.docx