文件名称:SCMIPS

  • 所属分类:
  • 微处理器(ARM/PowerPC等)
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 131kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 赵**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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使用verilog代码描述了一种简单的单周期MIPS处理器实现,并在ModelSim SE6.5c调试通过。-The verilog code describes a simple, single-cycle MIPS processor implementation, and debugging through in ModelSim SE6.5c,.
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下载文件列表





SCMIPS

......\memfile.dat

......\SCMIPS.cr.mti

......\SCMIPS.mpf

......\SCMIPS.v

......\SCMIPS.v.bak

......\testdata

......\........\memfile.dat

......\........\mipstest.asm

......\vsim.wlf

......\work

......\....\adder

......\....\.....\verilog.asm

......\....\.....\verilog.rw

......\....\.....\_primary.dat

......\....\.....\_primary.dbs

......\....\.....\_primary.vhd

......\....\alu

......\....\aludec

......\....\......\verilog.asm

......\....\......\verilog.rw

......\....\......\_primary.dat

......\....\......\_primary.dbs

......\....\......\_primary.vhd

......\....\...\verilog.asm

......\....\...\verilog.rw

......\....\...\_primary.dat

......\....\...\_primary.dbs

......\....\...\_primary.vhd

......\....\controller

......\....\..........\verilog.asm

......\....\..........\verilog.rw

......\....\..........\_primary.dat

......\....\..........\_primary.dbs

......\....\..........\_primary.vhd

......\....\datapath

......\....\........\verilog.asm

......\....\........\verilog.rw

......\....\........\_primary.dat

......\....\........\_primary.dbs

......\....\........\_primary.vhd

......\....\dmem

......\....\....\verilog.asm

......\....\....\verilog.rw

......\....\....\_primary.dat

......\....\....\_primary.dbs

......\....\....\_primary.vhd

......\....\flopr

......\....\.....\verilog.asm

......\....\.....\verilog.rw

......\....\.....\_primary.dat

......\....\.....\_primary.dbs

......\....\.....\_primary.vhd

......\....\imem

......\....\....\verilog.asm

......\....\....\verilog.rw

......\....\....\_primary.dat

......\....\....\_primary.dbs

......\....\....\_primary.vhd

......\....\maindec

......\....\.......\verilog.asm

......\....\.......\verilog.rw

......\....\.......\_primary.dat

......\....\.......\_primary.dbs

......\....\.......\_primary.vhd

......\....\mips

......\....\....\verilog.asm

......\....\....\verilog.rw

......\....\....\_primary.dat

......\....\....\_primary.dbs

......\....\....\_primary.vhd

......\....\mux2

......\....\....\verilog.asm

......\....\....\verilog.rw

......\....\....\_primary.dat

......\....\....\_primary.dbs

......\....\....\_primary.vhd

......\....\regfile

......\....\.......\verilog.asm

......\....\.......\verilog.rw

......\....\.......\_primary.dat

......\....\.......\_primary.dbs

......\....\.......\_primary.vhd

......\....\signext

......\....\.......\verilog.asm

......\....\.......\verilog.rw

......\....\.......\_primary.dat

......\....\.......\_primary.dbs

......\....\.......\_primary.vhd

......\....\sl2

......\....\...\verilog.asm

......\....\...\verilog.rw

......\....\...\_primary.dat

......\....\...\_primary.dbs

......\....\...\_primary.vhd

......\....\testbench

......\....\.........\verilog.asm

......\....\.........\verilog.rw

......\....\.........\_primary.dat

......\....\.........\_primary.dbs

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